2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device Tree for ARC HS Development Kit
14 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 compatible = "snps,hsdk";
24 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
37 compatible = "snps,archs38";
44 compatible = "snps,archs38";
51 compatible = "snps,archs38";
58 compatible = "snps,archs38";
64 input_clk: input-clk {
66 compatible = "fixed-clock";
67 clock-frequency = <33333333>;
70 cpu_intc: cpu-interrupt-controller {
71 compatible = "snps,archs-intc";
73 #interrupt-cells = <1>;
76 idu_intc: idu-interrupt-controller {
77 compatible = "snps,archs-idu-intc";
79 #interrupt-cells = <1>;
80 interrupt-parent = <&cpu_intc>;
84 compatible = "snps,archs-pct";
87 /* TIMER0 with interrupt for clockevent */
89 compatible = "snps,arc-timer";
91 interrupt-parent = <&cpu_intc>;
95 /* 64-bit Global Free Running Counter */
97 compatible = "snps,archs-timer-gfrc";
102 compatible = "simple-bus";
103 #address-cells = <1>;
105 interrupt-parent = <&idu_intc>;
107 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
109 cgu_rst: reset-controller@8a0 {
110 compatible = "snps,hsdk-reset";
112 reg = <0x8a0 0x4>, <0xff0 0x4>;
115 core_clk: core-clk@0 {
116 compatible = "snps,hsdk-core-pll-clock";
117 reg = <0x00 0x10>, <0x14b8 0x4>;
119 clocks = <&input_clk>;
122 * Set initial core pll output frequency to 1GHz.
123 * It will be applied at the core pll driver probing
126 assigned-clocks = <&core_clk>;
127 assigned-clock-rates = <1000000000>;
130 serial: serial@5000 {
131 compatible = "snps,dw-apb-uart";
132 reg = <0x5000 0x100>;
133 clock-frequency = <33330000>;
141 compatible = "fixed-clock";
142 clock-frequency = <400000000>;
146 mmcclk_ciu: mmcclk-ciu {
147 compatible = "fixed-clock";
149 * DW sdio controller has external ciu clock divider
150 * controlled via register in SDIO IP. Due to its
151 * unexpected default value (it should divide by 1
152 * but it divides by 8) SDIO IP uses wrong clock and
153 * works unstable (see STAR 9001204800)
154 * We switched to the minimum possible value of the
155 * divisor (div-by-2) in HSDK platform code.
156 * So add temporary fix and change clock frequency
157 * to 50000000 Hz until we fix dw sdio driver itself.
159 clock-frequency = <50000000>;
163 mmcclk_biu: mmcclk-biu {
164 compatible = "fixed-clock";
165 clock-frequency = <400000000>;
169 gpu_core_clk: gpu-core-clk {
170 compatible = "fixed-clock";
171 clock-frequency = <400000000>;
175 gpu_dma_clk: gpu-dma-clk {
176 compatible = "fixed-clock";
177 clock-frequency = <400000000>;
181 gpu_cfg_clk: gpu-cfg-clk {
182 compatible = "fixed-clock";
183 clock-frequency = <200000000>;
187 dmac_core_clk: dmac-core-clk {
188 compatible = "fixed-clock";
189 clock-frequency = <400000000>;
193 dmac_cfg_clk: dmac-gpu-cfg-clk {
194 compatible = "fixed-clock";
195 clock-frequency = <200000000>;
199 gmac: ethernet@8000 {
200 #interrupt-cells = <1>;
201 compatible = "snps,dwmac";
202 reg = <0x8000 0x2000>;
204 interrupt-names = "macirq";
207 snps,multicast-filter-bins = <256>;
209 clock-names = "stmmaceth";
210 phy-handle = <&phy0>;
211 resets = <&cgu_rst HSDK_ETH_RESET>;
212 reset-names = "stmmaceth";
213 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
216 tx-fifo-depth = <4096>;
217 rx-fifo-depth = <4096>;
220 #address-cells = <1>;
222 compatible = "snps,dwmac-mdio";
223 phy0: ethernet-phy@0 {
230 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
231 reg = <0x60000 0x100>;
233 resets = <&cgu_rst HSDK_USB_RESET>;
238 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
239 reg = <0x40000 0x100>;
241 resets = <&cgu_rst HSDK_USB_RESET>;
246 compatible = "altr,socfpga-dw-mshc";
247 reg = <0xa000 0x400>;
250 card-detect-delay = <200>;
251 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
252 clock-names = "biu", "ciu";
258 creg_gpio: gpio@14b0 {
259 compatible = "snps,creg-gpio-hsdk";
267 compatible = "snps,dw-apb-gpio";
269 #address-cells = <1>;
272 gpio_port_a: gpio-controller@0 {
273 compatible = "snps,dw-apb-gpio-port";
276 snps,nr-gpios = <24>;
282 compatible = "vivante,gc";
283 reg = <0x90000 0x4000>;
284 clocks = <&gpu_dma_clk>,
288 clock-names = "bus", "reg", "core", "shader";
293 compatible = "snps,axi-dma-1.01a";
294 reg = <0x80000 0x400>;
296 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
297 clock-names = "core-clk", "cfgr-clk";
300 snps,dma-masters = <2>;
301 snps,data-width = <3>;
302 snps,block-size = <4096 4096 4096 4096>;
303 snps,priority = <0 1 2 3>;
304 snps,axi-max-burst-len = <16>;
309 #address-cells = <2>;
311 device_type = "memory";
312 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
313 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */