2 * Support for peripherals on the AXS10x mainboard
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 compatible = "simple-bus";
16 ranges = <0x00000000 0xe0000000 0x10000000>;
17 interrupt-parent = <&mb_intc>;
19 i2sclk: i2sclk@100a0 {
20 compatible = "snps,axs10x-i2s-pll-clock";
22 clocks = <&i2spll_clk>;
27 i2spll_clk: i2spll_clk {
28 compatible = "fixed-clock";
29 clock-frequency = <27000000>;
34 compatible = "fixed-clock";
35 clock-frequency = <50000000>;
40 compatible = "fixed-clock";
41 clock-frequency = <50000000>;
46 compatible = "fixed-clock";
47 clock-frequency = <50000000>;
53 #interrupt-cells = <1>;
54 compatible = "snps,dwmac";
55 reg = < 0x18000 0x2000 >;
57 interrupt-names = "macirq";
61 clock-names = "stmmaceth";
66 compatible = "generic-ehci";
67 reg = < 0x40000 0x100 >;
72 compatible = "generic-ohci";
73 reg = < 0x60000 0x100 >;
78 * According to DW Mobile Storage databook it is required
79 * to use "Hold Register" if card is enumerated in SDR12 or
82 * Utilization of "Hold Register" is already implemented via
83 * dw_mci_pltfm_prepare_command() which in its turn gets
84 * used through dw_mci_drv_data->prepare_command call-back.
85 * This call-back is used in Altera Socfpga platform and so
86 * we may reuse it saying that we're compatible with their
87 * "altr,socfpga-dw-mshc".
89 * Most probably "Hold Register" utilization is platform-
90 * independent requirement which means that single unified
91 * "snps,dw-mshc" should be enough for all users of DW MMC once
92 * dw_mci_pltfm_prepare_command() is used in generic platform
96 compatible = "altr,socfpga-dw-mshc";
97 reg = < 0x15000 0x400 >;
100 card-detect-delay = < 200 >;
101 clocks = <&apbclk>, <&mmcclk>;
102 clock-names = "biu", "ciu";
108 compatible = "snps,dw-apb-uart";
109 reg = <0x20000 0x100>;
110 clock-frequency = <33333333>;
118 compatible = "snps,dw-apb-uart";
119 reg = <0x21000 0x100>;
120 clock-frequency = <33333333>;
127 /* UART muxed with USB data port (ttyS3) */
129 compatible = "snps,dw-apb-uart";
130 reg = <0x22000 0x100>;
131 clock-frequency = <33333333>;
139 compatible = "snps,designware-i2c";
140 reg = <0x1d000 0x100>;
141 clock-frequency = <400000>;
147 compatible = "snps,designware-i2c";
148 reg = <0x1e000 0x100>;
149 clock-frequency = <400000>;
155 compatible = "snps,designware-i2c";
156 #address-cells = <1>;
158 reg = <0x1f000 0x100>;
159 clock-frequency = <400000>;
164 compatible = "24c01";
170 compatible = "24c04";
177 compatible = "snps,dw-apb-gpio";
178 reg = <0x13000 0x1000>;
179 #address-cells = <1>;
182 gpio0_banka: gpio-controller@0 {
183 compatible = "snps,dw-apb-gpio-port";
186 snps,nr-gpios = <32>;
190 gpio0_bankb: gpio-controller@1 {
191 compatible = "snps,dw-apb-gpio-port";
198 gpio0_bankc: gpio-controller@2 {
199 compatible = "snps,dw-apb-gpio-port";
208 compatible = "snps,dw-apb-gpio";
209 reg = <0x14000 0x1000>;
210 #address-cells = <1>;
213 gpio1_banka: gpio-controller@0 {
214 compatible = "snps,dw-apb-gpio-port";
217 snps,nr-gpios = <30>;
221 gpio1_bankb: gpio-controller@1 {
222 compatible = "snps,dw-apb-gpio-port";
225 snps,nr-gpios = <10>;
229 gpio1_bankc: gpio-controller@2 {
230 compatible = "snps,dw-apb-gpio-port";