1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_CPU_CACHE_ALIASING
10 select ARCH_HAS_CACHE_LINE_SIZE
11 select ARCH_HAS_DEBUG_VM_PGTABLE
12 select ARCH_HAS_DMA_PREP_COHERENT
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SETUP_DMA_OPS
15 select ARCH_HAS_SYNC_DMA_FOR_CPU
16 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
17 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
18 select ARCH_32BIT_OFF_T
19 select BUILDTIME_TABLE_SORT
20 select CLONE_BACKWARDS
22 select DMA_DIRECT_REMAP
23 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
25 select GENERIC_IRQ_SHOW
26 select GENERIC_PCI_IOMAP
27 select GENERIC_PENDING_IRQ if SMP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_IOREMAP
31 select GENERIC_STRNCPY_FROM_USER if MMU
32 select GENERIC_STRNLEN_USER if MMU
34 select HAVE_ARCH_TRACEHOOK
35 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
36 select HAVE_DEBUG_STACKOVERFLOW
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_IOREMAP_PROT
39 select HAVE_KERNEL_GZIP
40 select HAVE_KERNEL_LZMA
42 select HAVE_KRETPROBES
43 select HAVE_REGS_AND_STACK_ACCESS_API
44 select HAVE_MOD_ARCH_SPECIFIC
45 select HAVE_PERF_EVENTS
46 select HAVE_SYSCALL_TRACEPOINTS
48 select LOCK_MM_AND_FIND_VMA
49 select MODULES_USE_ELF_RELA
51 select OF_EARLY_FLATTREE
52 select PCI_SYSCALL if PCI
53 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
54 select TRACE_IRQFLAGS_SUPPORT
56 config LOCKDEP_SUPPORT
59 config SCHED_OMIT_FRAME_POINTER
65 config ARCH_FLATMEM_ENABLE
74 config GENERIC_CALIBRATE_DELAY
77 config GENERIC_HWEIGHT
80 config STACKTRACE_SUPPORT
84 menu "ARC Architecture Configuration"
86 menu "ARC Platform/SoC/Board"
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
95 prompt "ARC Instruction Set"
100 select CPU_NO_EFFICIENT_FFS
102 The original ARC ISA of ARC600/700 cores
106 select ARC_TIMERS_64BIT
108 ISA for the Next Generation ARC-HS cores
112 menu "ARC CPU Configuration"
116 default ARC_CPU_770 if ISA_ARCOMPACT
117 default ARC_CPU_HS if ISA_ARCV2
121 depends on ISA_ARCOMPACT
124 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
125 This core has a bunch of cool new features:
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
127 Shared Address Spaces (for sharing TLB entries in MMU)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
135 Support for ARC HS38x Cores based on ARCv2 ISA
136 The notable features are:
137 - SMP configurations of up to 4 cores with coherency
138 - Optional L2 Cache and IO-Coherency
139 - Revised Interrupt Architecture (multiple priorites, reg banks,
140 auto stack switch, auto regfile save/restore)
141 - MMUv4 (PIPT dcache, Huge Pages)
143 * 64bit load/store: LDD, STD
144 * Hardware assisted divide/remainder: DIV, REM
145 * Function prologue/epilogue: ENTER_S, LEAVE_S
146 * IRQ enable/disable: CLRI, SETI
147 * pop count: FFS, FLS
148 * SETcc, BMSKN, XBFU...
153 string "Override default -mcpu compiler flag"
156 Override default -mcpu=xxx compiler flag (which is set depending on
157 the ISA version) with the specified value.
158 NOTE: If specified flag isn't supported by current compiler the
159 ISA default value will be used as a fallback.
161 config CPU_BIG_ENDIAN
162 bool "Enable Big Endian Mode"
164 Build kernel for Big Endian Mode of ARC CPU
167 bool "Symmetric Multi-Processing"
168 select ARC_MCIP if ISA_ARCV2
170 This enables support for systems with more than one CPU.
175 int "Maximum number of CPUs (2-4096)"
179 config ARC_SMP_HALT_ON_RESET
180 bool "Enable Halt-on-reset boot mode"
182 In SMP configuration cores can be configured as Halt-on-reset
183 or they could all start at same time. For Halt-on-reset, non
184 masters are parked until Master kicks them so they can start off
185 at designated entry point. For other case, all jump to common
186 entry point and spin wait for Master's signal.
191 bool "ARConnect Multicore IP (MCIP) Support "
195 This IP block enables SMP in ARC-HS38 cores.
196 It provides for cross-core interrupts, multi-core debug
197 hardware semaphores, shared memory,....
200 bool "Enable Cache Support"
205 config ARC_CACHE_LINE_SHIFT
206 int "Cache Line Length (as power of 2)"
210 Starting with ARC700 4.9, Cache line length is configurable,
211 This option specifies "N", with Line-len = 2 power N
212 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
213 Linux only supports same line lengths for I and D caches.
215 config ARC_HAS_ICACHE
216 bool "Use Instruction Cache"
219 config ARC_HAS_DCACHE
220 bool "Use Data Cache"
223 config ARC_CACHE_PAGES
224 bool "Per Page Cache Control"
226 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
228 This can be used to over-ride the global I/D Cache Enable on a
229 per-page basis (but only for pages accessed via MMU such as
230 Kernel Virtual address or User Virtual Address)
231 TLB entries have a per-page Cache Enable Bit.
232 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
233 Global DISABLE + Per Page ENABLE won't work
240 Single Cycle RAMS to store Fast Path Code
243 int "ICCM Size in KB"
245 depends on ARC_HAS_ICCM
250 Single Cycle RAMS to store Fast Path Data
253 int "DCCM Size in KB"
255 depends on ARC_HAS_DCCM
258 hex "DCCM map address"
260 depends on ARC_HAS_DCCM
264 default ARC_MMU_V3 if ISA_ARCOMPACT
265 default ARC_MMU_V4 if ISA_ARCV2
269 depends on ISA_ARCOMPACT
271 Introduced with ARC700 4.10: New Features
272 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
273 Shared Address Spaces (SASID)
283 prompt "MMU Page Size"
284 default ARC_PAGE_SIZE_8K
286 config ARC_PAGE_SIZE_8K
288 select HAVE_PAGE_SIZE_8KB
290 Choose between 8k vs 16k
292 config ARC_PAGE_SIZE_16K
293 select HAVE_PAGE_SIZE_16KB
296 config ARC_PAGE_SIZE_4K
298 select HAVE_PAGE_SIZE_4KB
299 depends on ARC_MMU_V3 || ARC_MMU_V4
304 prompt "MMU Super Page Size"
305 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
306 default ARC_HUGEPAGE_2M
308 config ARC_HUGEPAGE_2M
311 config ARC_HUGEPAGE_16M
316 config PGTABLE_LEVELS
317 int "Number of Page table levels"
320 config ARC_COMPACT_IRQ_LEVELS
321 depends on ISA_ARCOMPACT
322 bool "Setup Timer IRQ as high Priority"
323 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
326 config ARC_FPU_SAVE_RESTORE
327 bool "Enable FPU state persistence across context switch"
329 ARCompact FPU has internal registers to assist with Double precision
330 Floating Point operations. There are control and stauts registers
331 for floating point exceptions and rounding modes. These are
332 preserved across task context switch when enabled.
338 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
340 depends on !ARC_CANT_LLSC
343 bool "Insn: SWAPE (endian-swap)"
348 config ARC_USE_UNALIGNED_MEM_ACCESS
349 bool "Enable unaligned access in HW"
351 select HAVE_EFFICIENT_UNALIGNED_ACCESS
353 The ARC HS architecture supports unaligned memory access
354 which is disabled by default. Enable unaligned access in
355 hardware and use software to use it
358 bool "Insn: 64bit LDD/STD"
360 Enable gcc to generate 64-bit load/store instructions
361 ISA mandates even/odd registers to allow encoding of two
362 dest operands with 2 possible source operands.
365 config ARC_HAS_DIV_REM
366 bool "Insn: div, divu, rem, remu"
369 config ARC_HAS_ACCL_REGS
370 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
373 Depending on the configuration, CPU can contain accumulator reg-pair
374 (also referred to as r58:r59). These can also be used by gcc as GPR so
375 kernel needs to save/restore per process
377 config ARC_DSP_HANDLED
380 config ARC_DSP_SAVE_RESTORE_REGS
387 Depending on the configuration, CPU can contain DSP registers
388 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
389 Below are options describing how to handle these registers in
390 interrupt entry / exit and in context switch.
393 bool "No DSP extension presence in HW"
395 No DSP extension presence in HW
397 config ARC_DSP_KERNEL
398 bool "DSP extension in HW, no support for userspace"
399 select ARC_HAS_ACCL_REGS
400 select ARC_DSP_HANDLED
402 DSP extension presence in HW, no support for DSP-enabled userspace
403 applications. We don't save / restore DSP registers and only do
404 some minimal preparations so userspace won't be able to break kernel
406 config ARC_DSP_USERSPACE
407 bool "Support DSP for userspace apps"
408 select ARC_HAS_ACCL_REGS
409 select ARC_DSP_HANDLED
410 select ARC_DSP_SAVE_RESTORE_REGS
412 DSP extension presence in HW, support save / restore DSP registers to
413 run DSP-enabled userspace applications
415 config ARC_DSP_AGU_USERSPACE
416 bool "Support DSP with AGU for userspace apps"
417 select ARC_HAS_ACCL_REGS
418 select ARC_DSP_HANDLED
419 select ARC_DSP_SAVE_RESTORE_REGS
421 DSP and AGU extensions presence in HW, support save / restore DSP
422 and AGU registers to run DSP-enabled userspace applications
425 config ARC_IRQ_NO_AUTOSAVE
426 bool "Disable hardware autosave regfile on interrupts"
429 On HS cores, taken interrupt auto saves the regfile on stack.
430 This is programmable and can be optionally disabled in which case
431 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
433 config ARC_LPB_DISABLE
434 bool "Disable loop buffer (LPB)"
436 On HS cores, loop buffer (LPB) is programmable in runtime and can
437 be optionally disabled.
441 endmenu # "ARC CPU Configuration"
443 config LINUX_LINK_BASE
444 hex "Kernel link address"
447 ARC700 divides the 32 bit phy address space into two equal halves
448 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
449 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
450 Typically Linux kernel is linked at the start of untransalted addr,
451 hence the default value of 0x8zs.
452 However some customers have peripherals mapped at this addr, so
453 Linux needs to be scooted a bit.
454 If you don't know what the above means, leave this setting alone.
455 This needs to match memory start address specified in Device Tree
457 config LINUX_RAM_BASE
458 hex "RAM base address"
459 default LINUX_LINK_BASE
461 By default Linux is linked at base of RAM. However in some special
462 cases (such as HSDK), Linux can't be linked at start of DDR, hence
466 bool "High Memory Support"
467 select HAVE_ARCH_PFN_VALID
470 With ARC 2G:2G address split, only upper 2G is directly addressable by
471 kernel. Enable this to potentially allow access to rest of 2G and PAE
475 bool "Support for the 40-bit Physical Address Extension"
478 select PHYS_ADDR_T_64BIT
480 Enable access to physical memory beyond 4G, only supported on
481 ARC cores with 40 bit Physical Addressing support
483 config ARC_KVADDR_SIZE
484 int "Kernel Virtual Address Space size (MB)"
488 The kernel address space is carved out of 256MB of translated address
489 space for catering to vmalloc, modules, pkmap, fixmap. This however may
490 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
491 this to be stretched to 512 MB (by extending into the reserved
494 config ARC_CURR_IN_REG
495 bool "cache current task pointer in gp"
498 This reserves gp register to point to Current Task in
499 kernel mode eliding memory access for each access
502 config ARC_EMUL_UNALIGNED
503 bool "Emulate unaligned memory access (userspace only)"
504 select SYSCTL_ARCH_UNALIGN_NO_WARN
505 select SYSCTL_ARCH_UNALIGN_ALLOW
506 depends on ISA_ARCOMPACT
508 This enables misaligned 16 & 32 bit memory access from user space.
509 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
510 potential bugs in code
513 int "Timer Frequency"
516 config ARC_METAWARE_HLINK
517 bool "Support for Metaware debugger assisted Host access"
519 This options allows a Linux userland apps to directly access
520 host file system (open/creat/read/write etc) with help from
521 Metaware Debugger. This can come in handy for Linux-host communication
522 when there is no real usable peripheral such as EMAC.
530 config ARC_DW2_UNWIND
531 bool "Enable DWARF specific kernel stack unwind"
535 Compiles the kernel with DWARF unwind information and can be used
536 to get stack backtraces.
538 If you say Y here the resulting kernel image will be slightly larger
539 but not slower, and it will give very useful debugging information.
540 If you don't debug the kernel, you can say N, but we may not be able
541 to solve problems without frame unwind information
543 config ARC_DBG_JUMP_LABEL
544 bool "Paranoid checks in Static Keys (jump labels) code"
545 depends on JUMP_LABEL
546 default y if STATIC_KEYS_SELFTEST
548 Enable paranoid checks and self-test of both ARC-specific and generic
549 part of static keys (jump labels) related code.
552 config ARC_BUILTIN_DTB_NAME
553 string "Built in DTB"
555 Set the name of the DTB to embed in the vmlinux binary
556 Leaving it blank selects the minimal "skeleton" dtb
558 endmenu # "ARC Architecture Configuration"
560 config ARCH_FORCE_MAX_ORDER
561 int "Maximum zone order"
562 default "11" if ARC_HUGEPAGE_16M
565 source "kernel/power/Kconfig"