1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_CACHE_LINE_SIZE
10 select ARCH_HAS_DEBUG_VM_PGTABLE
11 select ARCH_HAS_DMA_PREP_COHERENT
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_SETUP_DMA_OPS
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select ARCH_32BIT_OFF_T
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
21 select DMA_DIRECT_REMAP
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_TRACEHOOK
31 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
32 select HAVE_DEBUG_STACKOVERFLOW
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_IOREMAP_PROT
35 select HAVE_KERNEL_GZIP
36 select HAVE_KERNEL_LZMA
38 select HAVE_KRETPROBES
39 select HAVE_MOD_ARCH_SPECIFIC
40 select HAVE_PERF_EVENTS
42 select MODULES_USE_ELF_RELA
44 select OF_EARLY_FLATTREE
45 select PCI_SYSCALL if PCI
46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
47 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
48 select TRACE_IRQFLAGS_SUPPORT
50 config LOCKDEP_SUPPORT
53 config SCHED_OMIT_FRAME_POINTER
59 config ARCH_FLATMEM_ENABLE
68 config GENERIC_CALIBRATE_DELAY
71 config GENERIC_HWEIGHT
74 config STACKTRACE_SUPPORT
78 menu "ARC Architecture Configuration"
80 menu "ARC Platform/SoC/Board"
82 source "arch/arc/plat-tb10x/Kconfig"
83 source "arch/arc/plat-axs10x/Kconfig"
84 source "arch/arc/plat-hsdk/Kconfig"
89 prompt "ARC Instruction Set"
94 select CPU_NO_EFFICIENT_FFS
96 The original ARC ISA of ARC600/700 cores
100 select ARC_TIMERS_64BIT
102 ISA for the Next Generation ARC-HS cores
106 menu "ARC CPU Configuration"
110 default ARC_CPU_770 if ISA_ARCOMPACT
111 default ARC_CPU_HS if ISA_ARCV2
115 depends on ISA_ARCOMPACT
118 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
119 This core has a bunch of cool new features:
120 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
121 Shared Address Spaces (for sharing TLB entries in MMU)
122 -Caches: New Prog Model, Region Flush
123 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
129 Support for ARC HS38x Cores based on ARCv2 ISA
130 The notable features are:
131 - SMP configurations of up to 4 cores with coherency
132 - Optional L2 Cache and IO-Coherency
133 - Revised Interrupt Architecture (multiple priorites, reg banks,
134 auto stack switch, auto regfile save/restore)
135 - MMUv4 (PIPT dcache, Huge Pages)
137 * 64bit load/store: LDD, STD
138 * Hardware assisted divide/remainder: DIV, REM
139 * Function prologue/epilogue: ENTER_S, LEAVE_S
140 * IRQ enable/disable: CLRI, SETI
141 * pop count: FFS, FLS
142 * SETcc, BMSKN, XBFU...
147 string "Override default -mcpu compiler flag"
150 Override default -mcpu=xxx compiler flag (which is set depending on
151 the ISA version) with the specified value.
152 NOTE: If specified flag isn't supported by current compiler the
153 ISA default value will be used as a fallback.
155 config CPU_BIG_ENDIAN
156 bool "Enable Big Endian Mode"
158 Build kernel for Big Endian Mode of ARC CPU
161 bool "Symmetric Multi-Processing"
162 select ARC_MCIP if ISA_ARCV2
164 This enables support for systems with more than one CPU.
169 int "Maximum number of CPUs (2-4096)"
173 config ARC_SMP_HALT_ON_RESET
174 bool "Enable Halt-on-reset boot mode"
176 In SMP configuration cores can be configured as Halt-on-reset
177 or they could all start at same time. For Halt-on-reset, non
178 masters are parked until Master kicks them so they can start off
179 at designated entry point. For other case, all jump to common
180 entry point and spin wait for Master's signal.
185 bool "ARConnect Multicore IP (MCIP) Support "
189 This IP block enables SMP in ARC-HS38 cores.
190 It provides for cross-core interrupts, multi-core debug
191 hardware semaphores, shared memory,....
194 bool "Enable Cache Support"
199 config ARC_CACHE_LINE_SHIFT
200 int "Cache Line Length (as power of 2)"
204 Starting with ARC700 4.9, Cache line length is configurable,
205 This option specifies "N", with Line-len = 2 power N
206 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
207 Linux only supports same line lengths for I and D caches.
209 config ARC_HAS_ICACHE
210 bool "Use Instruction Cache"
213 config ARC_HAS_DCACHE
214 bool "Use Data Cache"
217 config ARC_CACHE_PAGES
218 bool "Per Page Cache Control"
220 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
222 This can be used to over-ride the global I/D Cache Enable on a
223 per-page basis (but only for pages accessed via MMU such as
224 Kernel Virtual address or User Virtual Address)
225 TLB entries have a per-page Cache Enable Bit.
226 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
227 Global DISABLE + Per Page ENABLE won't work
229 config ARC_CACHE_VIPT_ALIASING
230 bool "Support VIPT Aliasing D$"
231 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
238 Single Cycle RAMS to store Fast Path Code
241 int "ICCM Size in KB"
243 depends on ARC_HAS_ICCM
248 Single Cycle RAMS to store Fast Path Data
251 int "DCCM Size in KB"
253 depends on ARC_HAS_DCCM
256 hex "DCCM map address"
258 depends on ARC_HAS_DCCM
262 default ARC_MMU_V3 if ISA_ARCOMPACT
263 default ARC_MMU_V4 if ISA_ARCV2
267 depends on ISA_ARCOMPACT
269 Introduced with ARC700 4.10: New Features
270 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
271 Shared Address Spaces (SASID)
281 prompt "MMU Page Size"
282 default ARC_PAGE_SIZE_8K
284 config ARC_PAGE_SIZE_8K
287 Choose between 8k vs 16k
289 config ARC_PAGE_SIZE_16K
292 config ARC_PAGE_SIZE_4K
294 depends on ARC_MMU_V3 || ARC_MMU_V4
299 prompt "MMU Super Page Size"
300 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
301 default ARC_HUGEPAGE_2M
303 config ARC_HUGEPAGE_2M
306 config ARC_HUGEPAGE_16M
311 config PGTABLE_LEVELS
312 int "Number of Page table levels"
315 config ARC_COMPACT_IRQ_LEVELS
316 depends on ISA_ARCOMPACT
317 bool "Setup Timer IRQ as high Priority"
318 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
321 config ARC_FPU_SAVE_RESTORE
322 bool "Enable FPU state persistence across context switch"
324 ARCompact FPU has internal registers to assist with Double precision
325 Floating Point operations. There are control and stauts registers
326 for floating point exceptions and rounding modes. These are
327 preserved across task context switch when enabled.
333 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
335 depends on !ARC_CANT_LLSC
338 bool "Insn: SWAPE (endian-swap)"
343 config ARC_USE_UNALIGNED_MEM_ACCESS
344 bool "Enable unaligned access in HW"
346 select HAVE_EFFICIENT_UNALIGNED_ACCESS
348 The ARC HS architecture supports unaligned memory access
349 which is disabled by default. Enable unaligned access in
350 hardware and use software to use it
353 bool "Insn: 64bit LDD/STD"
355 Enable gcc to generate 64-bit load/store instructions
356 ISA mandates even/odd registers to allow encoding of two
357 dest operands with 2 possible source operands.
360 config ARC_HAS_DIV_REM
361 bool "Insn: div, divu, rem, remu"
364 config ARC_HAS_ACCL_REGS
365 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
368 Depending on the configuration, CPU can contain accumulator reg-pair
369 (also referred to as r58:r59). These can also be used by gcc as GPR so
370 kernel needs to save/restore per process
372 config ARC_DSP_HANDLED
375 config ARC_DSP_SAVE_RESTORE_REGS
382 Depending on the configuration, CPU can contain DSP registers
383 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
384 Below are options describing how to handle these registers in
385 interrupt entry / exit and in context switch.
388 bool "No DSP extension presence in HW"
390 No DSP extension presence in HW
392 config ARC_DSP_KERNEL
393 bool "DSP extension in HW, no support for userspace"
394 select ARC_HAS_ACCL_REGS
395 select ARC_DSP_HANDLED
397 DSP extension presence in HW, no support for DSP-enabled userspace
398 applications. We don't save / restore DSP registers and only do
399 some minimal preparations so userspace won't be able to break kernel
401 config ARC_DSP_USERSPACE
402 bool "Support DSP for userspace apps"
403 select ARC_HAS_ACCL_REGS
404 select ARC_DSP_HANDLED
405 select ARC_DSP_SAVE_RESTORE_REGS
407 DSP extension presence in HW, support save / restore DSP registers to
408 run DSP-enabled userspace applications
410 config ARC_DSP_AGU_USERSPACE
411 bool "Support DSP with AGU for userspace apps"
412 select ARC_HAS_ACCL_REGS
413 select ARC_DSP_HANDLED
414 select ARC_DSP_SAVE_RESTORE_REGS
416 DSP and AGU extensions presence in HW, support save / restore DSP
417 and AGU registers to run DSP-enabled userspace applications
420 config ARC_IRQ_NO_AUTOSAVE
421 bool "Disable hardware autosave regfile on interrupts"
424 On HS cores, taken interrupt auto saves the regfile on stack.
425 This is programmable and can be optionally disabled in which case
426 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
428 config ARC_LPB_DISABLE
429 bool "Disable loop buffer (LPB)"
431 On HS cores, loop buffer (LPB) is programmable in runtime and can
432 be optionally disabled.
436 endmenu # "ARC CPU Configuration"
438 config LINUX_LINK_BASE
439 hex "Kernel link address"
442 ARC700 divides the 32 bit phy address space into two equal halves
443 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
444 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
445 Typically Linux kernel is linked at the start of untransalted addr,
446 hence the default value of 0x8zs.
447 However some customers have peripherals mapped at this addr, so
448 Linux needs to be scooted a bit.
449 If you don't know what the above means, leave this setting alone.
450 This needs to match memory start address specified in Device Tree
452 config LINUX_RAM_BASE
453 hex "RAM base address"
454 default LINUX_LINK_BASE
456 By default Linux is linked at base of RAM. However in some special
457 cases (such as HSDK), Linux can't be linked at start of DDR, hence
461 bool "High Memory Support"
462 select HAVE_ARCH_PFN_VALID
465 With ARC 2G:2G address split, only upper 2G is directly addressable by
466 kernel. Enable this to potentially allow access to rest of 2G and PAE
470 bool "Support for the 40-bit Physical Address Extension"
473 select PHYS_ADDR_T_64BIT
475 Enable access to physical memory beyond 4G, only supported on
476 ARC cores with 40 bit Physical Addressing support
478 config ARC_KVADDR_SIZE
479 int "Kernel Virtual Address Space size (MB)"
483 The kernel address space is carved out of 256MB of translated address
484 space for catering to vmalloc, modules, pkmap, fixmap. This however may
485 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
486 this to be stretched to 512 MB (by extending into the reserved
489 config ARC_CURR_IN_REG
490 bool "Dedicate Register r25 for current_task pointer"
493 This reserved Register R25 to point to Current Task in
494 kernel mode. This saves memory access for each such access
497 config ARC_EMUL_UNALIGNED
498 bool "Emulate unaligned memory access (userspace only)"
499 select SYSCTL_ARCH_UNALIGN_NO_WARN
500 select SYSCTL_ARCH_UNALIGN_ALLOW
501 depends on ISA_ARCOMPACT
503 This enables misaligned 16 & 32 bit memory access from user space.
504 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
505 potential bugs in code
508 int "Timer Frequency"
511 config ARC_METAWARE_HLINK
512 bool "Support for Metaware debugger assisted Host access"
514 This options allows a Linux userland apps to directly access
515 host file system (open/creat/read/write etc) with help from
516 Metaware Debugger. This can come in handy for Linux-host communication
517 when there is no real usable peripheral such as EMAC.
525 config ARC_DW2_UNWIND
526 bool "Enable DWARF specific kernel stack unwind"
530 Compiles the kernel with DWARF unwind information and can be used
531 to get stack backtraces.
533 If you say Y here the resulting kernel image will be slightly larger
534 but not slower, and it will give very useful debugging information.
535 If you don't debug the kernel, you can say N, but we may not be able
536 to solve problems without frame unwind information
538 config ARC_DBG_JUMP_LABEL
539 bool "Paranoid checks in Static Keys (jump labels) code"
540 depends on JUMP_LABEL
541 default y if STATIC_KEYS_SELFTEST
543 Enable paranoid checks and self-test of both ARC-specific and generic
544 part of static keys (jump labels) related code.
547 config ARC_BUILTIN_DTB_NAME
548 string "Built in DTB"
550 Set the name of the DTB to embed in the vmlinux binary
551 Leaving it blank selects the minimal "skeleton" dtb
553 endmenu # "ARC Architecture Configuration"
555 config FORCE_MAX_ZONEORDER
556 int "Maximum zone order"
557 default "12" if ARC_HUGEPAGE_16M
560 source "kernel/power/Kconfig"