2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_HAS_DMA_COHERENT_TO_PFN
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_HAS_SG_CHAIN
17 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
18 select BUILDTIME_EXTABLE_SORT
19 select CLONE_BACKWARDS
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 select GENERIC_CLOCKEVENTS
24 select GENERIC_FIND_FIRST_BIT
25 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
26 select GENERIC_IRQ_SHOW
27 select GENERIC_PCI_IOMAP
28 select GENERIC_PENDING_IRQ if SMP
29 select GENERIC_SCHED_CLOCK
30 select GENERIC_SMP_IDLE_THREAD
32 select HAVE_ARCH_TRACEHOOK
33 select HAVE_DEBUG_STACKOVERFLOW
34 select HAVE_FUTEX_CMPXCHG if FUTEX
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_IOREMAP_PROT
37 select HAVE_KERNEL_GZIP
38 select HAVE_KERNEL_LZMA
40 select HAVE_KRETPROBES
41 select HAVE_MOD_ARCH_SPECIFIC
43 select HAVE_PERF_EVENTS
44 select HANDLE_DOMAIN_IRQ
46 select MODULES_USE_ELF_RELA
48 select OF_EARLY_FLATTREE
49 select OF_RESERVED_MEM
50 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
52 config ARCH_HAS_CACHE_LINE_SIZE
58 config TRACE_IRQFLAGS_SUPPORT
61 config LOCKDEP_SUPPORT
64 config SCHED_OMIT_FRAME_POINTER
70 config RWSEM_GENERIC_SPINLOCK
73 config ARCH_DISCONTIGMEM_ENABLE
76 config ARCH_FLATMEM_ENABLE
85 config GENERIC_CALIBRATE_DELAY
88 config GENERIC_HWEIGHT
91 config STACKTRACE_SUPPORT
95 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
99 menu "ARC Architecture Configuration"
101 menu "ARC Platform/SoC/Board"
103 source "arch/arc/plat-tb10x/Kconfig"
104 source "arch/arc/plat-axs10x/Kconfig"
105 #New platform adds here
106 source "arch/arc/plat-eznps/Kconfig"
107 source "arch/arc/plat-hsdk/Kconfig"
112 prompt "ARC Instruction Set"
117 select CPU_NO_EFFICIENT_FFS
119 The original ARC ISA of ARC600/700 cores
123 select ARC_TIMERS_64BIT
125 ISA for the Next Generation ARC-HS cores
129 menu "ARC CPU Configuration"
133 default ARC_CPU_770 if ISA_ARCOMPACT
134 default ARC_CPU_HS if ISA_ARCV2
142 Support for ARC750 core
148 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
149 This core has a bunch of cool new features:
150 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
151 Shared Address Spaces (for sharing TLB entries in MMU)
152 -Caches: New Prog Model, Region Flush
153 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
161 Support for ARC HS38x Cores based on ARCv2 ISA
162 The notable features are:
163 - SMP configurations of upto 4 core with coherency
164 - Optional L2 Cache and IO-Coherency
165 - Revised Interrupt Architecture (multiple priorites, reg banks,
166 auto stack switch, auto regfile save/restore)
167 - MMUv4 (PIPT dcache, Huge Pages)
169 * 64bit load/store: LDD, STD
170 * Hardware assisted divide/remainder: DIV, REM
171 * Function prologue/epilogue: ENTER_S, LEAVE_S
172 * IRQ enable/disable: CLRI, SETI
173 * pop count: FFS, FLS
174 * SETcc, BMSKN, XBFU...
178 config CPU_BIG_ENDIAN
179 bool "Enable Big Endian Mode"
181 Build kernel for Big Endian Mode of ARC CPU
184 bool "Symmetric Multi-Processing"
185 select ARC_MCIP if ISA_ARCV2
187 This enables support for systems with more than one CPU.
192 int "Maximum number of CPUs (2-4096)"
196 config ARC_SMP_HALT_ON_RESET
197 bool "Enable Halt-on-reset boot mode"
198 default y if ARC_UBOOT_SUPPORT
200 In SMP configuration cores can be configured as Halt-on-reset
201 or they could all start at same time. For Halt-on-reset, non
202 masters are parked until Master kicks them so they can start of
203 at designated entry point. For other case, all jump to common
204 entry point and spin wait for Master's signal.
209 bool "ARConnect Multicore IP (MCIP) Support "
213 This IP block enables SMP in ARC-HS38 cores.
214 It provides for cross-core interrupts, multi-core debug
215 hardware semaphores, shared memory,....
218 bool "Enable Cache Support"
223 config ARC_CACHE_LINE_SHIFT
224 int "Cache Line Length (as power of 2)"
228 Starting with ARC700 4.9, Cache line length is configurable,
229 This option specifies "N", with Line-len = 2 power N
230 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
231 Linux only supports same line lengths for I and D caches.
233 config ARC_HAS_ICACHE
234 bool "Use Instruction Cache"
237 config ARC_HAS_DCACHE
238 bool "Use Data Cache"
241 config ARC_CACHE_PAGES
242 bool "Per Page Cache Control"
244 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
246 This can be used to over-ride the global I/D Cache Enable on a
247 per-page basis (but only for pages accessed via MMU such as
248 Kernel Virtual address or User Virtual Address)
249 TLB entries have a per-page Cache Enable Bit.
250 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
251 Global DISABLE + Per Page ENABLE won't work
253 config ARC_CACHE_VIPT_ALIASING
254 bool "Support VIPT Aliasing D$"
255 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
262 Single Cycle RAMS to store Fast Path Code
265 int "ICCM Size in KB"
267 depends on ARC_HAS_ICCM
272 Single Cycle RAMS to store Fast Path Data
275 int "DCCM Size in KB"
277 depends on ARC_HAS_DCCM
280 hex "DCCM map address"
282 depends on ARC_HAS_DCCM
286 default ARC_MMU_V3 if ARC_CPU_770
287 default ARC_MMU_V2 if ARC_CPU_750D
288 default ARC_MMU_V4 if ARC_CPU_HS
300 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
301 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
305 depends on ARC_CPU_770
307 Introduced with ARC700 4.10: New Features
308 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
309 Shared Address Spaces (SASID)
321 prompt "MMU Page Size"
322 default ARC_PAGE_SIZE_8K
324 config ARC_PAGE_SIZE_8K
327 Choose between 8k vs 16k
329 config ARC_PAGE_SIZE_16K
331 depends on ARC_MMU_V3 || ARC_MMU_V4
333 config ARC_PAGE_SIZE_4K
335 depends on ARC_MMU_V3 || ARC_MMU_V4
340 prompt "MMU Super Page Size"
341 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
342 default ARC_HUGEPAGE_2M
344 config ARC_HUGEPAGE_2M
347 config ARC_HUGEPAGE_16M
353 int "Maximum NUMA Nodes (as a power of 2)"
354 default "0" if !DISCONTIGMEM
355 default "1" if DISCONTIGMEM
356 depends on NEED_MULTIPLE_NODES
358 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
363 config ARC_COMPACT_IRQ_LEVELS
364 bool "Setup Timer IRQ as high Priority"
365 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
368 config ARC_FPU_SAVE_RESTORE
369 bool "Enable FPU state persistence across context switch"
371 Double Precision Floating Point unit had dedicated regs which
372 need to be saved/restored across context-switch.
373 Note that ARC FPU is overly simplistic, unlike say x86, which has
374 hardware pieces to allow software to conditionally save/restore,
375 based on actual usage of FPU by a task. Thus our implemn does
376 this for all tasks in system.
384 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
386 depends on !ARC_CANT_LLSC
389 bool "Insn: SWAPE (endian-swap)"
395 bool "Insn: 64bit LDD/STD"
397 Enable gcc to generate 64-bit load/store instructions
398 ISA mandates even/odd registers to allow encoding of two
399 dest operands with 2 possible source operands.
402 config ARC_HAS_DIV_REM
403 bool "Insn: div, divu, rem, remu"
406 config ARC_HAS_ACCL_REGS
407 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
410 Depending on the configuration, CPU can contain accumulator reg-pair
411 (also referred to as r58:r59). These can also be used by gcc as GPR so
412 kernel needs to save/restore per process
416 endmenu # "ARC CPU Configuration"
418 config LINUX_LINK_BASE
419 hex "Kernel link address"
422 ARC700 divides the 32 bit phy address space into two equal halves
423 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
424 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
425 Typically Linux kernel is linked at the start of untransalted addr,
426 hence the default value of 0x8zs.
427 However some customers have peripherals mapped at this addr, so
428 Linux needs to be scooted a bit.
429 If you don't know what the above means, leave this setting alone.
430 This needs to match memory start address specified in Device Tree
432 config LINUX_RAM_BASE
433 hex "RAM base address"
434 default LINUX_LINK_BASE
436 By default Linux is linked at base of RAM. However in some special
437 cases (such as HSDK), Linux can't be linked at start of DDR, hence
441 bool "High Memory Support"
442 select ARCH_DISCONTIGMEM_ENABLE
444 With ARC 2G:2G address split, only upper 2G is directly addressable by
445 kernel. Enable this to potentially allow access to rest of 2G and PAE
449 bool "Support for the 40-bit Physical Address Extension"
452 select PHYS_ADDR_T_64BIT
454 Enable access to physical memory beyond 4G, only supported on
455 ARC cores with 40 bit Physical Addressing support
457 config ARC_KVADDR_SIZE
458 int "Kernel Virtual Address Space size (MB)"
462 The kernel address space is carved out of 256MB of translated address
463 space for catering to vmalloc, modules, pkmap, fixmap. This however may
464 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
465 this to be stretched to 512 MB (by extending into the reserved
468 config ARC_CURR_IN_REG
469 bool "Dedicate Register r25 for current_task pointer"
472 This reserved Register R25 to point to Current Task in
473 kernel mode. This saves memory access for each such access
476 config ARC_EMUL_UNALIGNED
477 bool "Emulate unaligned memory access (userspace only)"
478 select SYSCTL_ARCH_UNALIGN_NO_WARN
479 select SYSCTL_ARCH_UNALIGN_ALLOW
480 depends on ISA_ARCOMPACT
482 This enables misaligned 16 & 32 bit memory access from user space.
483 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
484 potential bugs in code
487 int "Timer Frequency"
490 config ARC_METAWARE_HLINK
491 bool "Support for Metaware debugger assisted Host access"
493 This options allows a Linux userland apps to directly access
494 host file system (open/creat/read/write etc) with help from
495 Metaware Debugger. This can come in handy for Linux-host communication
496 when there is no real usable peripheral such as EMAC.
504 config ARC_DW2_UNWIND
505 bool "Enable DWARF specific kernel stack unwind"
509 Compiles the kernel with DWARF unwind information and can be used
510 to get stack backtraces.
512 If you say Y here the resulting kernel image will be slightly larger
513 but not slower, and it will give very useful debugging information.
514 If you don't debug the kernel, you can say N, but we may not be able
515 to solve problems without frame unwind information
517 config ARC_DBG_TLB_PARANOIA
518 bool "Paranoia Checks in Low Level TLB Handlers"
522 config ARC_UBOOT_SUPPORT
523 bool "Support uboot arg Handling"
525 ARC Linux by default checks for uboot provided args as pointers to
526 external cmdline or DTB. This however breaks in absence of uboot,
527 when booting from Metaware debugger directly, as the registers are
528 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
529 registers look like uboot args to kernel which then chokes.
530 So only enable the uboot arg checking/processing if users are sure
531 of uboot being in play.
533 config ARC_BUILTIN_DTB_NAME
534 string "Built in DTB"
536 Set the name of the DTB to embed in the vmlinux binary
537 Leaving it blank selects the minimal "skeleton" dtb
539 endmenu # "ARC Architecture Configuration"
541 config FORCE_MAX_ZONEORDER
542 int "Maximum zone order"
543 default "12" if ARC_HUGEPAGE_16M
549 bool "PCI support" if MIGHT_HAVE_PCI
551 PCI is the name of a bus system, i.e., the way the CPU talks to
552 the other stuff inside your box. Find out if your board/platform
555 Note: PCIe support for Synopsys Device will be available only
556 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
562 source "drivers/pci/Kconfig"
566 source "kernel/power/Kconfig"