1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_DEBUG_VM_PGTABLE
10 select ARCH_HAS_DMA_PREP_COHERENT
11 select ARCH_HAS_PTE_SPECIAL
12 select ARCH_HAS_SETUP_DMA_OPS
13 select ARCH_HAS_SYNC_DMA_FOR_CPU
14 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
16 select ARCH_32BIT_OFF_T
17 select BUILDTIME_TABLE_SORT
18 select CLONE_BACKWARDS
20 select DMA_DIRECT_REMAP
21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
22 select GENERIC_CLOCKEVENTS
23 select GENERIC_FIND_FIRST_BIT
24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
25 select GENERIC_IRQ_SHOW
26 select GENERIC_PCI_IOMAP
27 select GENERIC_PENDING_IRQ if SMP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_DEBUG_STACKOVERFLOW
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_FUTEX_CMPXCHG if FUTEX
35 select HAVE_IOREMAP_PROT
36 select HAVE_KERNEL_GZIP
37 select HAVE_KERNEL_LZMA
39 select HAVE_KRETPROBES
40 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select HANDLE_DOMAIN_IRQ
45 select MODULES_USE_ELF_RELA
47 select OF_EARLY_FLATTREE
48 select PCI_SYSCALL if PCI
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
52 config ARCH_HAS_CACHE_LINE_SIZE
55 config TRACE_IRQFLAGS_SUPPORT
58 config LOCKDEP_SUPPORT
61 config SCHED_OMIT_FRAME_POINTER
67 config ARCH_DISCONTIGMEM_ENABLE
70 config ARCH_FLATMEM_ENABLE
79 config GENERIC_CALIBRATE_DELAY
82 config GENERIC_HWEIGHT
85 config STACKTRACE_SUPPORT
89 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
93 menu "ARC Architecture Configuration"
95 menu "ARC Platform/SoC/Board"
97 source "arch/arc/plat-tb10x/Kconfig"
98 source "arch/arc/plat-axs10x/Kconfig"
99 #New platform adds here
100 source "arch/arc/plat-eznps/Kconfig"
101 source "arch/arc/plat-hsdk/Kconfig"
106 prompt "ARC Instruction Set"
111 select CPU_NO_EFFICIENT_FFS
113 The original ARC ISA of ARC600/700 cores
117 select ARC_TIMERS_64BIT
119 ISA for the Next Generation ARC-HS cores
123 menu "ARC CPU Configuration"
127 default ARC_CPU_770 if ISA_ARCOMPACT
128 default ARC_CPU_HS if ISA_ARCV2
136 Support for ARC750 core
142 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
143 This core has a bunch of cool new features:
144 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
145 Shared Address Spaces (for sharing TLB entries in MMU)
146 -Caches: New Prog Model, Region Flush
147 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
155 Support for ARC HS38x Cores based on ARCv2 ISA
156 The notable features are:
157 - SMP configurations of up to 4 cores with coherency
158 - Optional L2 Cache and IO-Coherency
159 - Revised Interrupt Architecture (multiple priorites, reg banks,
160 auto stack switch, auto regfile save/restore)
161 - MMUv4 (PIPT dcache, Huge Pages)
163 * 64bit load/store: LDD, STD
164 * Hardware assisted divide/remainder: DIV, REM
165 * Function prologue/epilogue: ENTER_S, LEAVE_S
166 * IRQ enable/disable: CLRI, SETI
167 * pop count: FFS, FLS
168 * SETcc, BMSKN, XBFU...
173 string "Override default -mcpu compiler flag"
176 Override default -mcpu=xxx compiler flag (which is set depending on
177 the ISA version) with the specified value.
178 NOTE: If specified flag isn't supported by current compiler the
179 ISA default value will be used as a fallback.
181 config CPU_BIG_ENDIAN
182 bool "Enable Big Endian Mode"
184 Build kernel for Big Endian Mode of ARC CPU
187 bool "Symmetric Multi-Processing"
188 select ARC_MCIP if ISA_ARCV2
190 This enables support for systems with more than one CPU.
195 int "Maximum number of CPUs (2-4096)"
199 config ARC_SMP_HALT_ON_RESET
200 bool "Enable Halt-on-reset boot mode"
202 In SMP configuration cores can be configured as Halt-on-reset
203 or they could all start at same time. For Halt-on-reset, non
204 masters are parked until Master kicks them so they can start off
205 at designated entry point. For other case, all jump to common
206 entry point and spin wait for Master's signal.
211 bool "ARConnect Multicore IP (MCIP) Support "
215 This IP block enables SMP in ARC-HS38 cores.
216 It provides for cross-core interrupts, multi-core debug
217 hardware semaphores, shared memory,....
220 bool "Enable Cache Support"
225 config ARC_CACHE_LINE_SHIFT
226 int "Cache Line Length (as power of 2)"
230 Starting with ARC700 4.9, Cache line length is configurable,
231 This option specifies "N", with Line-len = 2 power N
232 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
233 Linux only supports same line lengths for I and D caches.
235 config ARC_HAS_ICACHE
236 bool "Use Instruction Cache"
239 config ARC_HAS_DCACHE
240 bool "Use Data Cache"
243 config ARC_CACHE_PAGES
244 bool "Per Page Cache Control"
246 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
248 This can be used to over-ride the global I/D Cache Enable on a
249 per-page basis (but only for pages accessed via MMU such as
250 Kernel Virtual address or User Virtual Address)
251 TLB entries have a per-page Cache Enable Bit.
252 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
253 Global DISABLE + Per Page ENABLE won't work
255 config ARC_CACHE_VIPT_ALIASING
256 bool "Support VIPT Aliasing D$"
257 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
264 Single Cycle RAMS to store Fast Path Code
267 int "ICCM Size in KB"
269 depends on ARC_HAS_ICCM
274 Single Cycle RAMS to store Fast Path Data
277 int "DCCM Size in KB"
279 depends on ARC_HAS_DCCM
282 hex "DCCM map address"
284 depends on ARC_HAS_DCCM
288 default ARC_MMU_V3 if ARC_CPU_770
289 default ARC_MMU_V2 if ARC_CPU_750D
290 default ARC_MMU_V4 if ARC_CPU_HS
302 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
303 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
307 depends on ARC_CPU_770
309 Introduced with ARC700 4.10: New Features
310 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
311 Shared Address Spaces (SASID)
323 prompt "MMU Page Size"
324 default ARC_PAGE_SIZE_8K
326 config ARC_PAGE_SIZE_8K
329 Choose between 8k vs 16k
331 config ARC_PAGE_SIZE_16K
333 depends on ARC_MMU_V3 || ARC_MMU_V4
335 config ARC_PAGE_SIZE_4K
337 depends on ARC_MMU_V3 || ARC_MMU_V4
342 prompt "MMU Super Page Size"
343 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
344 default ARC_HUGEPAGE_2M
346 config ARC_HUGEPAGE_2M
349 config ARC_HUGEPAGE_16M
355 int "Maximum NUMA Nodes (as a power of 2)"
356 default "0" if !DISCONTIGMEM
357 default "1" if DISCONTIGMEM
358 depends on NEED_MULTIPLE_NODES
360 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
363 config ARC_COMPACT_IRQ_LEVELS
364 depends on ISA_ARCOMPACT
365 bool "Setup Timer IRQ as high Priority"
366 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
369 config ARC_FPU_SAVE_RESTORE
370 bool "Enable FPU state persistence across context switch"
372 ARCompact FPU has internal registers to assist with Double precision
373 Floating Point operations. There are control and stauts registers
374 for floating point exceptions and rounding modes. These are
375 preserved across task context switch when enabled.
381 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
383 depends on !ARC_CANT_LLSC
386 bool "Insn: SWAPE (endian-swap)"
391 config ARC_USE_UNALIGNED_MEM_ACCESS
392 bool "Enable unaligned access in HW"
394 select HAVE_EFFICIENT_UNALIGNED_ACCESS
396 The ARC HS architecture supports unaligned memory access
397 which is disabled by default. Enable unaligned access in
398 hardware and use software to use it
401 bool "Insn: 64bit LDD/STD"
403 Enable gcc to generate 64-bit load/store instructions
404 ISA mandates even/odd registers to allow encoding of two
405 dest operands with 2 possible source operands.
408 config ARC_HAS_DIV_REM
409 bool "Insn: div, divu, rem, remu"
412 config ARC_HAS_ACCL_REGS
413 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
416 Depending on the configuration, CPU can contain accumulator reg-pair
417 (also referred to as r58:r59). These can also be used by gcc as GPR so
418 kernel needs to save/restore per process
420 config ARC_DSP_HANDLED
423 config ARC_DSP_SAVE_RESTORE_REGS
430 Depending on the configuration, CPU can contain DSP registers
431 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
432 Bellow is options describing how to handle these registers in
433 interrupt entry / exit and in context switch.
436 bool "No DSP extension presence in HW"
438 No DSP extension presence in HW
440 config ARC_DSP_KERNEL
441 bool "DSP extension in HW, no support for userspace"
442 select ARC_HAS_ACCL_REGS
443 select ARC_DSP_HANDLED
445 DSP extension presence in HW, no support for DSP-enabled userspace
446 applications. We don't save / restore DSP registers and only do
447 some minimal preparations so userspace won't be able to break kernel
449 config ARC_DSP_USERSPACE
450 bool "Support DSP for userspace apps"
451 select ARC_HAS_ACCL_REGS
452 select ARC_DSP_HANDLED
453 select ARC_DSP_SAVE_RESTORE_REGS
455 DSP extension presence in HW, support save / restore DSP registers to
456 run DSP-enabled userspace applications
458 config ARC_DSP_AGU_USERSPACE
459 bool "Support DSP with AGU for userspace apps"
460 select ARC_HAS_ACCL_REGS
461 select ARC_DSP_HANDLED
462 select ARC_DSP_SAVE_RESTORE_REGS
464 DSP and AGU extensions presence in HW, support save / restore DSP
465 and AGU registers to run DSP-enabled userspace applications
468 config ARC_IRQ_NO_AUTOSAVE
469 bool "Disable hardware autosave regfile on interrupts"
472 On HS cores, taken interrupt auto saves the regfile on stack.
473 This is programmable and can be optionally disabled in which case
474 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
476 config ARC_LPB_DISABLE
477 bool "Disable loop buffer (LPB)"
479 On HS cores, loop buffer (LPB) is programmable in runtime and can
480 be optionally disabled.
484 endmenu # "ARC CPU Configuration"
486 config LINUX_LINK_BASE
487 hex "Kernel link address"
490 ARC700 divides the 32 bit phy address space into two equal halves
491 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
492 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
493 Typically Linux kernel is linked at the start of untransalted addr,
494 hence the default value of 0x8zs.
495 However some customers have peripherals mapped at this addr, so
496 Linux needs to be scooted a bit.
497 If you don't know what the above means, leave this setting alone.
498 This needs to match memory start address specified in Device Tree
500 config LINUX_RAM_BASE
501 hex "RAM base address"
502 default LINUX_LINK_BASE
504 By default Linux is linked at base of RAM. However in some special
505 cases (such as HSDK), Linux can't be linked at start of DDR, hence
509 bool "High Memory Support"
510 select ARCH_DISCONTIGMEM_ENABLE
512 With ARC 2G:2G address split, only upper 2G is directly addressable by
513 kernel. Enable this to potentially allow access to rest of 2G and PAE
517 bool "Support for the 40-bit Physical Address Extension"
520 select PHYS_ADDR_T_64BIT
522 Enable access to physical memory beyond 4G, only supported on
523 ARC cores with 40 bit Physical Addressing support
525 config ARC_KVADDR_SIZE
526 int "Kernel Virtual Address Space size (MB)"
530 The kernel address space is carved out of 256MB of translated address
531 space for catering to vmalloc, modules, pkmap, fixmap. This however may
532 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
533 this to be stretched to 512 MB (by extending into the reserved
536 config ARC_CURR_IN_REG
537 bool "Dedicate Register r25 for current_task pointer"
540 This reserved Register R25 to point to Current Task in
541 kernel mode. This saves memory access for each such access
544 config ARC_EMUL_UNALIGNED
545 bool "Emulate unaligned memory access (userspace only)"
546 select SYSCTL_ARCH_UNALIGN_NO_WARN
547 select SYSCTL_ARCH_UNALIGN_ALLOW
548 depends on ISA_ARCOMPACT
550 This enables misaligned 16 & 32 bit memory access from user space.
551 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
552 potential bugs in code
555 int "Timer Frequency"
558 config ARC_METAWARE_HLINK
559 bool "Support for Metaware debugger assisted Host access"
561 This options allows a Linux userland apps to directly access
562 host file system (open/creat/read/write etc) with help from
563 Metaware Debugger. This can come in handy for Linux-host communication
564 when there is no real usable peripheral such as EMAC.
572 config ARC_DW2_UNWIND
573 bool "Enable DWARF specific kernel stack unwind"
577 Compiles the kernel with DWARF unwind information and can be used
578 to get stack backtraces.
580 If you say Y here the resulting kernel image will be slightly larger
581 but not slower, and it will give very useful debugging information.
582 If you don't debug the kernel, you can say N, but we may not be able
583 to solve problems without frame unwind information
585 config ARC_DBG_TLB_PARANOIA
586 bool "Paranoia Checks in Low Level TLB Handlers"
588 config ARC_DBG_JUMP_LABEL
589 bool "Paranoid checks in Static Keys (jump labels) code"
590 depends on JUMP_LABEL
591 default y if STATIC_KEYS_SELFTEST
593 Enable paranoid checks and self-test of both ARC-specific and generic
594 part of static keys (jump labels) related code.
597 config ARC_BUILTIN_DTB_NAME
598 string "Built in DTB"
600 Set the name of the DTB to embed in the vmlinux binary
601 Leaving it blank selects the minimal "skeleton" dtb
603 endmenu # "ARC Architecture Configuration"
605 config FORCE_MAX_ZONEORDER
606 int "Maximum zone order"
607 default "12" if ARC_HUGEPAGE_16M
610 source "kernel/power/Kconfig"