2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_HAS_DMA_COHERENT_TO_PFN
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select BUILDTIME_EXTABLE_SORT
18 select CLONE_BACKWARDS
20 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
21 select GENERIC_CLOCKEVENTS
22 select GENERIC_FIND_FIRST_BIT
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_TRACEHOOK
31 select HAVE_DEBUG_STACKOVERFLOW
32 select HAVE_FUTEX_CMPXCHG if FUTEX
33 select HAVE_GENERIC_DMA_COHERENT
34 select HAVE_IOREMAP_PROT
35 select HAVE_KERNEL_GZIP
36 select HAVE_KERNEL_LZMA
38 select HAVE_KRETPROBES
39 select HAVE_MOD_ARCH_SPECIFIC
41 select HAVE_PERF_EVENTS
42 select HANDLE_DOMAIN_IRQ
44 select MODULES_USE_ELF_RELA
46 select OF_EARLY_FLATTREE
47 select OF_RESERVED_MEM
48 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50 config ARCH_HAS_CACHE_LINE_SIZE
56 config TRACE_IRQFLAGS_SUPPORT
59 config LOCKDEP_SUPPORT
62 config SCHED_OMIT_FRAME_POINTER
68 config RWSEM_GENERIC_SPINLOCK
71 config ARCH_DISCONTIGMEM_ENABLE
74 config ARCH_FLATMEM_ENABLE
83 config GENERIC_CALIBRATE_DELAY
86 config GENERIC_HWEIGHT
89 config STACKTRACE_SUPPORT
93 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
97 menu "ARC Architecture Configuration"
99 menu "ARC Platform/SoC/Board"
101 source "arch/arc/plat-tb10x/Kconfig"
102 source "arch/arc/plat-axs10x/Kconfig"
103 #New platform adds here
104 source "arch/arc/plat-eznps/Kconfig"
105 source "arch/arc/plat-hsdk/Kconfig"
110 prompt "ARC Instruction Set"
115 select CPU_NO_EFFICIENT_FFS
117 The original ARC ISA of ARC600/700 cores
121 select ARC_TIMERS_64BIT
123 ISA for the Next Generation ARC-HS cores
127 menu "ARC CPU Configuration"
131 default ARC_CPU_770 if ISA_ARCOMPACT
132 default ARC_CPU_HS if ISA_ARCV2
140 Support for ARC750 core
146 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
147 This core has a bunch of cool new features:
148 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
149 Shared Address Spaces (for sharing TLB entries in MMU)
150 -Caches: New Prog Model, Region Flush
151 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
159 Support for ARC HS38x Cores based on ARCv2 ISA
160 The notable features are:
161 - SMP configurations of upto 4 core with coherency
162 - Optional L2 Cache and IO-Coherency
163 - Revised Interrupt Architecture (multiple priorites, reg banks,
164 auto stack switch, auto regfile save/restore)
165 - MMUv4 (PIPT dcache, Huge Pages)
167 * 64bit load/store: LDD, STD
168 * Hardware assisted divide/remainder: DIV, REM
169 * Function prologue/epilogue: ENTER_S, LEAVE_S
170 * IRQ enable/disable: CLRI, SETI
171 * pop count: FFS, FLS
172 * SETcc, BMSKN, XBFU...
176 config CPU_BIG_ENDIAN
177 bool "Enable Big Endian Mode"
179 Build kernel for Big Endian Mode of ARC CPU
182 bool "Symmetric Multi-Processing"
183 select ARC_MCIP if ISA_ARCV2
185 This enables support for systems with more than one CPU.
190 int "Maximum number of CPUs (2-4096)"
194 config ARC_SMP_HALT_ON_RESET
195 bool "Enable Halt-on-reset boot mode"
196 default y if ARC_UBOOT_SUPPORT
198 In SMP configuration cores can be configured as Halt-on-reset
199 or they could all start at same time. For Halt-on-reset, non
200 masters are parked until Master kicks them so they can start of
201 at designated entry point. For other case, all jump to common
202 entry point and spin wait for Master's signal.
207 bool "ARConnect Multicore IP (MCIP) Support "
211 This IP block enables SMP in ARC-HS38 cores.
212 It provides for cross-core interrupts, multi-core debug
213 hardware semaphores, shared memory,....
216 bool "Enable Cache Support"
221 config ARC_CACHE_LINE_SHIFT
222 int "Cache Line Length (as power of 2)"
226 Starting with ARC700 4.9, Cache line length is configurable,
227 This option specifies "N", with Line-len = 2 power N
228 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
229 Linux only supports same line lengths for I and D caches.
231 config ARC_HAS_ICACHE
232 bool "Use Instruction Cache"
235 config ARC_HAS_DCACHE
236 bool "Use Data Cache"
239 config ARC_CACHE_PAGES
240 bool "Per Page Cache Control"
242 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
244 This can be used to over-ride the global I/D Cache Enable on a
245 per-page basis (but only for pages accessed via MMU such as
246 Kernel Virtual address or User Virtual Address)
247 TLB entries have a per-page Cache Enable Bit.
248 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
249 Global DISABLE + Per Page ENABLE won't work
251 config ARC_CACHE_VIPT_ALIASING
252 bool "Support VIPT Aliasing D$"
253 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
260 Single Cycle RAMS to store Fast Path Code
263 int "ICCM Size in KB"
265 depends on ARC_HAS_ICCM
270 Single Cycle RAMS to store Fast Path Data
273 int "DCCM Size in KB"
275 depends on ARC_HAS_DCCM
278 hex "DCCM map address"
280 depends on ARC_HAS_DCCM
284 default ARC_MMU_V3 if ARC_CPU_770
285 default ARC_MMU_V2 if ARC_CPU_750D
286 default ARC_MMU_V4 if ARC_CPU_HS
298 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
299 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
303 depends on ARC_CPU_770
305 Introduced with ARC700 4.10: New Features
306 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
307 Shared Address Spaces (SASID)
319 prompt "MMU Page Size"
320 default ARC_PAGE_SIZE_8K
322 config ARC_PAGE_SIZE_8K
325 Choose between 8k vs 16k
327 config ARC_PAGE_SIZE_16K
329 depends on ARC_MMU_V3 || ARC_MMU_V4
331 config ARC_PAGE_SIZE_4K
333 depends on ARC_MMU_V3 || ARC_MMU_V4
338 prompt "MMU Super Page Size"
339 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
340 default ARC_HUGEPAGE_2M
342 config ARC_HUGEPAGE_2M
345 config ARC_HUGEPAGE_16M
351 int "Maximum NUMA Nodes (as a power of 2)"
352 default "0" if !DISCONTIGMEM
353 default "1" if DISCONTIGMEM
354 depends on NEED_MULTIPLE_NODES
356 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
361 config ARC_COMPACT_IRQ_LEVELS
362 bool "Setup Timer IRQ as high Priority"
363 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
366 config ARC_FPU_SAVE_RESTORE
367 bool "Enable FPU state persistence across context switch"
369 Double Precision Floating Point unit had dedicated regs which
370 need to be saved/restored across context-switch.
371 Note that ARC FPU is overly simplistic, unlike say x86, which has
372 hardware pieces to allow software to conditionally save/restore,
373 based on actual usage of FPU by a task. Thus our implemn does
374 this for all tasks in system.
382 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
384 depends on !ARC_CANT_LLSC
387 bool "Insn: SWAPE (endian-swap)"
393 bool "Insn: 64bit LDD/STD"
395 Enable gcc to generate 64-bit load/store instructions
396 ISA mandates even/odd registers to allow encoding of two
397 dest operands with 2 possible source operands.
400 config ARC_HAS_DIV_REM
401 bool "Insn: div, divu, rem, remu"
404 config ARC_HAS_ACCL_REGS
405 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
408 Depending on the configuration, CPU can contain accumulator reg-pair
409 (also referred to as r58:r59). These can also be used by gcc as GPR so
410 kernel needs to save/restore per process
414 endmenu # "ARC CPU Configuration"
416 config LINUX_LINK_BASE
417 hex "Kernel link address"
420 ARC700 divides the 32 bit phy address space into two equal halves
421 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
422 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
423 Typically Linux kernel is linked at the start of untransalted addr,
424 hence the default value of 0x8zs.
425 However some customers have peripherals mapped at this addr, so
426 Linux needs to be scooted a bit.
427 If you don't know what the above means, leave this setting alone.
428 This needs to match memory start address specified in Device Tree
430 config LINUX_RAM_BASE
431 hex "RAM base address"
432 default LINUX_LINK_BASE
434 By default Linux is linked at base of RAM. However in some special
435 cases (such as HSDK), Linux can't be linked at start of DDR, hence
439 bool "High Memory Support"
440 select ARCH_DISCONTIGMEM_ENABLE
442 With ARC 2G:2G address split, only upper 2G is directly addressable by
443 kernel. Enable this to potentially allow access to rest of 2G and PAE
447 bool "Support for the 40-bit Physical Address Extension"
450 select PHYS_ADDR_T_64BIT
452 Enable access to physical memory beyond 4G, only supported on
453 ARC cores with 40 bit Physical Addressing support
455 config ARC_KVADDR_SIZE
456 int "Kernel Virtual Address Space size (MB)"
460 The kernel address space is carved out of 256MB of translated address
461 space for catering to vmalloc, modules, pkmap, fixmap. This however may
462 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
463 this to be stretched to 512 MB (by extending into the reserved
466 config ARC_CURR_IN_REG
467 bool "Dedicate Register r25 for current_task pointer"
470 This reserved Register R25 to point to Current Task in
471 kernel mode. This saves memory access for each such access
474 config ARC_EMUL_UNALIGNED
475 bool "Emulate unaligned memory access (userspace only)"
476 select SYSCTL_ARCH_UNALIGN_NO_WARN
477 select SYSCTL_ARCH_UNALIGN_ALLOW
478 depends on ISA_ARCOMPACT
480 This enables misaligned 16 & 32 bit memory access from user space.
481 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
482 potential bugs in code
485 int "Timer Frequency"
488 config ARC_METAWARE_HLINK
489 bool "Support for Metaware debugger assisted Host access"
491 This options allows a Linux userland apps to directly access
492 host file system (open/creat/read/write etc) with help from
493 Metaware Debugger. This can come in handy for Linux-host communication
494 when there is no real usable peripheral such as EMAC.
502 config ARC_DW2_UNWIND
503 bool "Enable DWARF specific kernel stack unwind"
507 Compiles the kernel with DWARF unwind information and can be used
508 to get stack backtraces.
510 If you say Y here the resulting kernel image will be slightly larger
511 but not slower, and it will give very useful debugging information.
512 If you don't debug the kernel, you can say N, but we may not be able
513 to solve problems without frame unwind information
515 config ARC_DBG_TLB_PARANOIA
516 bool "Paranoia Checks in Low Level TLB Handlers"
520 config ARC_UBOOT_SUPPORT
521 bool "Support uboot arg Handling"
523 ARC Linux by default checks for uboot provided args as pointers to
524 external cmdline or DTB. This however breaks in absence of uboot,
525 when booting from Metaware debugger directly, as the registers are
526 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
527 registers look like uboot args to kernel which then chokes.
528 So only enable the uboot arg checking/processing if users are sure
529 of uboot being in play.
531 config ARC_BUILTIN_DTB_NAME
532 string "Built in DTB"
534 Set the name of the DTB to embed in the vmlinux binary
535 Leaving it blank selects the minimal "skeleton" dtb
537 endmenu # "ARC Architecture Configuration"
539 config FORCE_MAX_ZONEORDER
540 int "Maximum zone order"
541 default "12" if ARC_HUGEPAGE_16M
547 bool "PCI support" if MIGHT_HAVE_PCI
549 PCI is the name of a bus system, i.e., the way the CPU talks to
550 the other stuff inside your box. Find out if your board/platform
553 Note: PCIe support for Synopsys Device will be available only
554 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
560 source "drivers/pci/Kconfig"
564 source "kernel/power/Kconfig"