1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_DEBUG_VM_PGTABLE
10 select ARCH_HAS_DMA_PREP_COHERENT
11 select ARCH_HAS_PTE_SPECIAL
12 select ARCH_HAS_SETUP_DMA_OPS
13 select ARCH_HAS_SYNC_DMA_FOR_CPU
14 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
16 select ARCH_32BIT_OFF_T
17 select BUILDTIME_TABLE_SORT
18 select CLONE_BACKWARDS
20 select DMA_DIRECT_REMAP
21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
22 select GENERIC_FIND_FIRST_BIT
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_TRACEHOOK
31 select HAVE_DEBUG_STACKOVERFLOW
32 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_FUTEX_CMPXCHG if FUTEX
34 select HAVE_IOREMAP_PROT
35 select HAVE_KERNEL_GZIP
36 select HAVE_KERNEL_LZMA
38 select HAVE_KRETPROBES
39 select HAVE_MOD_ARCH_SPECIFIC
40 select HAVE_PERF_EVENTS
41 select HANDLE_DOMAIN_IRQ
43 select MODULES_USE_ELF_RELA
45 select OF_EARLY_FLATTREE
46 select PCI_SYSCALL if PCI
47 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
48 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
51 config ARCH_HAS_CACHE_LINE_SIZE
54 config TRACE_IRQFLAGS_SUPPORT
57 config LOCKDEP_SUPPORT
60 config SCHED_OMIT_FRAME_POINTER
66 config ARCH_DISCONTIGMEM_ENABLE
70 config ARCH_FLATMEM_ENABLE
79 config GENERIC_CALIBRATE_DELAY
82 config GENERIC_HWEIGHT
85 config STACKTRACE_SUPPORT
89 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
93 menu "ARC Architecture Configuration"
95 menu "ARC Platform/SoC/Board"
97 source "arch/arc/plat-tb10x/Kconfig"
98 source "arch/arc/plat-axs10x/Kconfig"
99 source "arch/arc/plat-hsdk/Kconfig"
104 prompt "ARC Instruction Set"
109 select CPU_NO_EFFICIENT_FFS
111 The original ARC ISA of ARC600/700 cores
115 select ARC_TIMERS_64BIT
117 ISA for the Next Generation ARC-HS cores
121 menu "ARC CPU Configuration"
125 default ARC_CPU_770 if ISA_ARCOMPACT
126 default ARC_CPU_HS if ISA_ARCV2
134 Support for ARC750 core
140 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
141 This core has a bunch of cool new features:
142 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
143 Shared Address Spaces (for sharing TLB entries in MMU)
144 -Caches: New Prog Model, Region Flush
145 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
153 Support for ARC HS38x Cores based on ARCv2 ISA
154 The notable features are:
155 - SMP configurations of up to 4 cores with coherency
156 - Optional L2 Cache and IO-Coherency
157 - Revised Interrupt Architecture (multiple priorites, reg banks,
158 auto stack switch, auto regfile save/restore)
159 - MMUv4 (PIPT dcache, Huge Pages)
161 * 64bit load/store: LDD, STD
162 * Hardware assisted divide/remainder: DIV, REM
163 * Function prologue/epilogue: ENTER_S, LEAVE_S
164 * IRQ enable/disable: CLRI, SETI
165 * pop count: FFS, FLS
166 * SETcc, BMSKN, XBFU...
171 string "Override default -mcpu compiler flag"
174 Override default -mcpu=xxx compiler flag (which is set depending on
175 the ISA version) with the specified value.
176 NOTE: If specified flag isn't supported by current compiler the
177 ISA default value will be used as a fallback.
179 config CPU_BIG_ENDIAN
180 bool "Enable Big Endian Mode"
182 Build kernel for Big Endian Mode of ARC CPU
185 bool "Symmetric Multi-Processing"
186 select ARC_MCIP if ISA_ARCV2
188 This enables support for systems with more than one CPU.
193 int "Maximum number of CPUs (2-4096)"
197 config ARC_SMP_HALT_ON_RESET
198 bool "Enable Halt-on-reset boot mode"
200 In SMP configuration cores can be configured as Halt-on-reset
201 or they could all start at same time. For Halt-on-reset, non
202 masters are parked until Master kicks them so they can start off
203 at designated entry point. For other case, all jump to common
204 entry point and spin wait for Master's signal.
209 bool "ARConnect Multicore IP (MCIP) Support "
213 This IP block enables SMP in ARC-HS38 cores.
214 It provides for cross-core interrupts, multi-core debug
215 hardware semaphores, shared memory,....
218 bool "Enable Cache Support"
223 config ARC_CACHE_LINE_SHIFT
224 int "Cache Line Length (as power of 2)"
228 Starting with ARC700 4.9, Cache line length is configurable,
229 This option specifies "N", with Line-len = 2 power N
230 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
231 Linux only supports same line lengths for I and D caches.
233 config ARC_HAS_ICACHE
234 bool "Use Instruction Cache"
237 config ARC_HAS_DCACHE
238 bool "Use Data Cache"
241 config ARC_CACHE_PAGES
242 bool "Per Page Cache Control"
244 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
246 This can be used to over-ride the global I/D Cache Enable on a
247 per-page basis (but only for pages accessed via MMU such as
248 Kernel Virtual address or User Virtual Address)
249 TLB entries have a per-page Cache Enable Bit.
250 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
251 Global DISABLE + Per Page ENABLE won't work
253 config ARC_CACHE_VIPT_ALIASING
254 bool "Support VIPT Aliasing D$"
255 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
262 Single Cycle RAMS to store Fast Path Code
265 int "ICCM Size in KB"
267 depends on ARC_HAS_ICCM
272 Single Cycle RAMS to store Fast Path Data
275 int "DCCM Size in KB"
277 depends on ARC_HAS_DCCM
280 hex "DCCM map address"
282 depends on ARC_HAS_DCCM
286 default ARC_MMU_V3 if ARC_CPU_770
287 default ARC_MMU_V2 if ARC_CPU_750D
288 default ARC_MMU_V4 if ARC_CPU_HS
300 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
301 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
305 depends on ARC_CPU_770
307 Introduced with ARC700 4.10: New Features
308 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
309 Shared Address Spaces (SASID)
321 prompt "MMU Page Size"
322 default ARC_PAGE_SIZE_8K
324 config ARC_PAGE_SIZE_8K
327 Choose between 8k vs 16k
329 config ARC_PAGE_SIZE_16K
331 depends on ARC_MMU_V3 || ARC_MMU_V4
333 config ARC_PAGE_SIZE_4K
335 depends on ARC_MMU_V3 || ARC_MMU_V4
340 prompt "MMU Super Page Size"
341 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
342 default ARC_HUGEPAGE_2M
344 config ARC_HUGEPAGE_2M
347 config ARC_HUGEPAGE_16M
353 int "Maximum NUMA Nodes (as a power of 2)"
354 default "0" if !DISCONTIGMEM
355 default "1" if DISCONTIGMEM
356 depends on NEED_MULTIPLE_NODES
358 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
361 config ARC_COMPACT_IRQ_LEVELS
362 depends on ISA_ARCOMPACT
363 bool "Setup Timer IRQ as high Priority"
364 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
367 config ARC_FPU_SAVE_RESTORE
368 bool "Enable FPU state persistence across context switch"
370 ARCompact FPU has internal registers to assist with Double precision
371 Floating Point operations. There are control and stauts registers
372 for floating point exceptions and rounding modes. These are
373 preserved across task context switch when enabled.
379 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
381 depends on !ARC_CANT_LLSC
384 bool "Insn: SWAPE (endian-swap)"
389 config ARC_USE_UNALIGNED_MEM_ACCESS
390 bool "Enable unaligned access in HW"
392 select HAVE_EFFICIENT_UNALIGNED_ACCESS
394 The ARC HS architecture supports unaligned memory access
395 which is disabled by default. Enable unaligned access in
396 hardware and use software to use it
399 bool "Insn: 64bit LDD/STD"
401 Enable gcc to generate 64-bit load/store instructions
402 ISA mandates even/odd registers to allow encoding of two
403 dest operands with 2 possible source operands.
406 config ARC_HAS_DIV_REM
407 bool "Insn: div, divu, rem, remu"
410 config ARC_HAS_ACCL_REGS
411 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
414 Depending on the configuration, CPU can contain accumulator reg-pair
415 (also referred to as r58:r59). These can also be used by gcc as GPR so
416 kernel needs to save/restore per process
418 config ARC_DSP_HANDLED
421 config ARC_DSP_SAVE_RESTORE_REGS
428 Depending on the configuration, CPU can contain DSP registers
429 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
430 Bellow is options describing how to handle these registers in
431 interrupt entry / exit and in context switch.
434 bool "No DSP extension presence in HW"
436 No DSP extension presence in HW
438 config ARC_DSP_KERNEL
439 bool "DSP extension in HW, no support for userspace"
440 select ARC_HAS_ACCL_REGS
441 select ARC_DSP_HANDLED
443 DSP extension presence in HW, no support for DSP-enabled userspace
444 applications. We don't save / restore DSP registers and only do
445 some minimal preparations so userspace won't be able to break kernel
447 config ARC_DSP_USERSPACE
448 bool "Support DSP for userspace apps"
449 select ARC_HAS_ACCL_REGS
450 select ARC_DSP_HANDLED
451 select ARC_DSP_SAVE_RESTORE_REGS
453 DSP extension presence in HW, support save / restore DSP registers to
454 run DSP-enabled userspace applications
456 config ARC_DSP_AGU_USERSPACE
457 bool "Support DSP with AGU for userspace apps"
458 select ARC_HAS_ACCL_REGS
459 select ARC_DSP_HANDLED
460 select ARC_DSP_SAVE_RESTORE_REGS
462 DSP and AGU extensions presence in HW, support save / restore DSP
463 and AGU registers to run DSP-enabled userspace applications
466 config ARC_IRQ_NO_AUTOSAVE
467 bool "Disable hardware autosave regfile on interrupts"
470 On HS cores, taken interrupt auto saves the regfile on stack.
471 This is programmable and can be optionally disabled in which case
472 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
474 config ARC_LPB_DISABLE
475 bool "Disable loop buffer (LPB)"
477 On HS cores, loop buffer (LPB) is programmable in runtime and can
478 be optionally disabled.
482 endmenu # "ARC CPU Configuration"
484 config LINUX_LINK_BASE
485 hex "Kernel link address"
488 ARC700 divides the 32 bit phy address space into two equal halves
489 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
490 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
491 Typically Linux kernel is linked at the start of untransalted addr,
492 hence the default value of 0x8zs.
493 However some customers have peripherals mapped at this addr, so
494 Linux needs to be scooted a bit.
495 If you don't know what the above means, leave this setting alone.
496 This needs to match memory start address specified in Device Tree
498 config LINUX_RAM_BASE
499 hex "RAM base address"
500 default LINUX_LINK_BASE
502 By default Linux is linked at base of RAM. However in some special
503 cases (such as HSDK), Linux can't be linked at start of DDR, hence
507 bool "High Memory Support"
508 select HAVE_ARCH_PFN_VALID
511 With ARC 2G:2G address split, only upper 2G is directly addressable by
512 kernel. Enable this to potentially allow access to rest of 2G and PAE
516 bool "Support for the 40-bit Physical Address Extension"
519 select PHYS_ADDR_T_64BIT
521 Enable access to physical memory beyond 4G, only supported on
522 ARC cores with 40 bit Physical Addressing support
524 config ARC_KVADDR_SIZE
525 int "Kernel Virtual Address Space size (MB)"
529 The kernel address space is carved out of 256MB of translated address
530 space for catering to vmalloc, modules, pkmap, fixmap. This however may
531 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
532 this to be stretched to 512 MB (by extending into the reserved
535 config ARC_CURR_IN_REG
536 bool "Dedicate Register r25 for current_task pointer"
539 This reserved Register R25 to point to Current Task in
540 kernel mode. This saves memory access for each such access
543 config ARC_EMUL_UNALIGNED
544 bool "Emulate unaligned memory access (userspace only)"
545 select SYSCTL_ARCH_UNALIGN_NO_WARN
546 select SYSCTL_ARCH_UNALIGN_ALLOW
547 depends on ISA_ARCOMPACT
549 This enables misaligned 16 & 32 bit memory access from user space.
550 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
551 potential bugs in code
554 int "Timer Frequency"
557 config ARC_METAWARE_HLINK
558 bool "Support for Metaware debugger assisted Host access"
560 This options allows a Linux userland apps to directly access
561 host file system (open/creat/read/write etc) with help from
562 Metaware Debugger. This can come in handy for Linux-host communication
563 when there is no real usable peripheral such as EMAC.
571 config ARC_DW2_UNWIND
572 bool "Enable DWARF specific kernel stack unwind"
576 Compiles the kernel with DWARF unwind information and can be used
577 to get stack backtraces.
579 If you say Y here the resulting kernel image will be slightly larger
580 but not slower, and it will give very useful debugging information.
581 If you don't debug the kernel, you can say N, but we may not be able
582 to solve problems without frame unwind information
584 config ARC_DBG_TLB_PARANOIA
585 bool "Paranoia Checks in Low Level TLB Handlers"
587 config ARC_DBG_JUMP_LABEL
588 bool "Paranoid checks in Static Keys (jump labels) code"
589 depends on JUMP_LABEL
590 default y if STATIC_KEYS_SELFTEST
592 Enable paranoid checks and self-test of both ARC-specific and generic
593 part of static keys (jump labels) related code.
596 config ARC_BUILTIN_DTB_NAME
597 string "Built in DTB"
599 Set the name of the DTB to embed in the vmlinux binary
600 Leaving it blank selects the minimal "skeleton" dtb
602 endmenu # "ARC Architecture Configuration"
604 config FORCE_MAX_ZONEORDER
605 int "Maximum zone order"
606 default "12" if ARC_HUGEPAGE_16M
609 source "kernel/power/Kconfig"