2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_HAS_SG_CHAIN
13 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
14 select BUILDTIME_EXTABLE_SORT
15 select CLONE_BACKWARDS
17 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
18 select GENERIC_CLOCKEVENTS
19 select GENERIC_FIND_FIRST_BIT
20 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_PENDING_IRQ if SMP
24 select GENERIC_SMP_IDLE_THREAD
26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_FUTEX_CMPXCHG
28 select HAVE_IOREMAP_PROT
30 select HAVE_KRETPROBES
32 select HAVE_MOD_ARCH_SPECIFIC
34 select HAVE_PERF_EVENTS
35 select HANDLE_DOMAIN_IRQ
37 select MODULES_USE_ELF_RELA
40 select OF_EARLY_FLATTREE
41 select OF_RESERVED_MEM
42 select PERF_USE_VMALLOC
43 select HAVE_DEBUG_STACKOVERFLOW
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZMA
47 select ARCH_HAS_RAW_COPY_USER
52 config TRACE_IRQFLAGS_SUPPORT
55 config LOCKDEP_SUPPORT
58 config SCHED_OMIT_FRAME_POINTER
64 config RWSEM_GENERIC_SPINLOCK
67 config ARCH_DISCONTIGMEM_ENABLE
70 config ARCH_FLATMEM_ENABLE
79 config GENERIC_CALIBRATE_DELAY
82 config GENERIC_HWEIGHT
85 config STACKTRACE_SUPPORT
89 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
94 source "kernel/Kconfig.freezer"
96 menu "ARC Architecture Configuration"
98 menu "ARC Platform/SoC/Board"
100 source "arch/arc/plat-sim/Kconfig"
101 source "arch/arc/plat-tb10x/Kconfig"
102 source "arch/arc/plat-axs10x/Kconfig"
103 #New platform adds here
104 source "arch/arc/plat-eznps/Kconfig"
109 prompt "ARC Instruction Set"
110 default ISA_ARCOMPACT
114 select CPU_NO_EFFICIENT_FFS
116 The original ARC ISA of ARC600/700 cores
120 select ARC_TIMERS_64BIT
122 ISA for the Next Generation ARC-HS cores
126 menu "ARC CPU Configuration"
130 default ARC_CPU_770 if ISA_ARCOMPACT
131 default ARC_CPU_HS if ISA_ARCV2
139 Support for ARC750 core
145 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
146 This core has a bunch of cool new features:
147 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
148 Shared Address Spaces (for sharing TLB entires in MMU)
149 -Caches: New Prog Model, Region Flush
150 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
158 Support for ARC HS38x Cores based on ARCv2 ISA
159 The notable features are:
160 - SMP configurations of upto 4 core with coherency
161 - Optional L2 Cache and IO-Coherency
162 - Revised Interrupt Architecture (multiple priorites, reg banks,
163 auto stack switch, auto regfile save/restore)
164 - MMUv4 (PIPT dcache, Huge Pages)
166 * 64bit load/store: LDD, STD
167 * Hardware assisted divide/remainder: DIV, REM
168 * Function prologue/epilogue: ENTER_S, LEAVE_S
169 * IRQ enable/disable: CLRI, SETI
170 * pop count: FFS, FLS
171 * SETcc, BMSKN, XBFU...
175 config CPU_BIG_ENDIAN
176 bool "Enable Big Endian Mode"
179 Build kernel for Big Endian Mode of ARC CPU
182 bool "Symmetric Multi-Processing"
184 select ARC_MCIP if ISA_ARCV2
186 This enables support for systems with more than one CPU.
191 int "Maximum number of CPUs (2-4096)"
195 config ARC_SMP_HALT_ON_RESET
196 bool "Enable Halt-on-reset boot mode"
197 default y if ARC_UBOOT_SUPPORT
199 In SMP configuration cores can be configured as Halt-on-reset
200 or they could all start at same time. For Halt-on-reset, non
201 masters are parked until Master kicks them so they can start of
202 at designated entry point. For other case, all jump to common
203 entry point and spin wait for Master's signal.
208 bool "ARConnect Multicore IP (MCIP) Support "
212 This IP block enables SMP in ARC-HS38 cores.
213 It provides for cross-core interrupts, multi-core debug
214 hardware semaphores, shared memory,....
217 bool "Enable Cache Support"
222 config ARC_CACHE_LINE_SHIFT
223 int "Cache Line Length (as power of 2)"
227 Starting with ARC700 4.9, Cache line length is configurable,
228 This option specifies "N", with Line-len = 2 power N
229 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
230 Linux only supports same line lengths for I and D caches.
232 config ARC_HAS_ICACHE
233 bool "Use Instruction Cache"
236 config ARC_HAS_DCACHE
237 bool "Use Data Cache"
240 config ARC_CACHE_PAGES
241 bool "Per Page Cache Control"
243 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
245 This can be used to over-ride the global I/D Cache Enable on a
246 per-page basis (but only for pages accessed via MMU such as
247 Kernel Virtual address or User Virtual Address)
248 TLB entries have a per-page Cache Enable Bit.
249 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
250 Global DISABLE + Per Page ENABLE won't work
252 config ARC_CACHE_VIPT_ALIASING
253 bool "Support VIPT Aliasing D$"
254 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
262 Single Cycle RAMS to store Fast Path Code
266 int "ICCM Size in KB"
268 depends on ARC_HAS_ICCM
273 Single Cycle RAMS to store Fast Path Data
277 int "DCCM Size in KB"
279 depends on ARC_HAS_DCCM
282 hex "DCCM map address"
284 depends on ARC_HAS_DCCM
288 default ARC_MMU_V3 if ARC_CPU_770
289 default ARC_MMU_V2 if ARC_CPU_750D
290 default ARC_MMU_V4 if ARC_CPU_HS
302 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
303 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
307 depends on ARC_CPU_770
309 Introduced with ARC700 4.10: New Features
310 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
311 Shared Address Spaces (SASID)
323 prompt "MMU Page Size"
324 default ARC_PAGE_SIZE_8K
326 config ARC_PAGE_SIZE_8K
329 Choose between 8k vs 16k
331 config ARC_PAGE_SIZE_16K
333 depends on ARC_MMU_V3 || ARC_MMU_V4
335 config ARC_PAGE_SIZE_4K
337 depends on ARC_MMU_V3 || ARC_MMU_V4
342 prompt "MMU Super Page Size"
343 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
344 default ARC_HUGEPAGE_2M
346 config ARC_HUGEPAGE_2M
349 config ARC_HUGEPAGE_16M
355 int "Maximum NUMA Nodes (as a power of 2)"
356 default "0" if !DISCONTIGMEM
357 default "1" if DISCONTIGMEM
358 depends on NEED_MULTIPLE_NODES
360 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
365 config ARC_COMPACT_IRQ_LEVELS
366 bool "Setup Timer IRQ as high Priority"
368 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
371 config ARC_FPU_SAVE_RESTORE
372 bool "Enable FPU state persistence across context switch"
375 Double Precision Floating Point unit had dedictaed regs which
376 need to be saved/restored across context-switch.
377 Note that ARC FPU is overly simplistic, unlike say x86, which has
378 hardware pieces to allow software to conditionally save/restore,
379 based on actual usage of FPU by a task. Thus our implemn does
380 this for all tasks in system.
388 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
390 depends on !ARC_CANT_LLSC
393 bool "Insn: SWAPE (endian-swap)"
399 bool "Insn: 64bit LDD/STD"
401 Enable gcc to generate 64-bit load/store instructions
402 ISA mandates even/odd registers to allow encoding of two
403 dest operands with 2 possible source operands.
406 config ARC_HAS_DIV_REM
407 bool "Insn: div, divu, rem, remu"
412 endmenu # "ARC CPU Configuration"
414 config LINUX_LINK_BASE
415 hex "Linux Link Address"
418 ARC700 divides the 32 bit phy address space into two equal halves
419 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
420 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
421 Typically Linux kernel is linked at the start of untransalted addr,
422 hence the default value of 0x8zs.
423 However some customers have peripherals mapped at this addr, so
424 Linux needs to be scooted a bit.
425 If you don't know what the above means, leave this setting alone.
426 This needs to match memory start address specified in Device Tree
429 bool "High Memory Support"
430 select ARCH_DISCONTIGMEM_ENABLE
432 With ARC 2G:2G address split, only upper 2G is directly addressable by
433 kernel. Enable this to potentially allow access to rest of 2G and PAE
437 bool "Support for the 40-bit Physical Address Extension"
441 Enable access to physical memory beyond 4G, only supported on
442 ARC cores with 40 bit Physical Addressing support
444 config ARCH_PHYS_ADDR_T_64BIT
445 def_bool ARC_HAS_PAE40
447 config ARCH_DMA_ADDR_T_64BIT
450 config ARC_PLAT_NEEDS_PHYS_TO_DMA
453 config ARC_KVADDR_SIZE
454 int "Kernel Virtaul Address Space size (MB)"
458 The kernel address space is carved out of 256MB of translated address
459 space for catering to vmalloc, modules, pkmap, fixmap. This however may
460 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
461 this to be stretched to 512 MB (by extending into the reserved
464 config ARC_CURR_IN_REG
465 bool "Dedicate Register r25 for current_task pointer"
468 This reserved Register R25 to point to Current Task in
469 kernel mode. This saves memory access for each such access
472 config ARC_EMUL_UNALIGNED
473 bool "Emulate unaligned memory access (userspace only)"
475 select SYSCTL_ARCH_UNALIGN_NO_WARN
476 select SYSCTL_ARCH_UNALIGN_ALLOW
477 depends on ISA_ARCOMPACT
479 This enables misaligned 16 & 32 bit memory access from user space.
480 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
481 potential bugs in code
484 int "Timer Frequency"
487 config ARC_METAWARE_HLINK
488 bool "Support for Metaware debugger assisted Host access"
491 This options allows a Linux userland apps to directly access
492 host file system (open/creat/read/write etc) with help from
493 Metaware Debugger. This can come in handy for Linux-host communication
494 when there is no real usable peripheral such as EMAC.
502 config ARC_DW2_UNWIND
503 bool "Enable DWARF specific kernel stack unwind"
507 Compiles the kernel with DWARF unwind information and can be used
508 to get stack backtraces.
510 If you say Y here the resulting kernel image will be slightly larger
511 but not slower, and it will give very useful debugging information.
512 If you don't debug the kernel, you can say N, but we may not be able
513 to solve problems without frame unwind information
515 config ARC_DBG_TLB_PARANOIA
516 bool "Paranoia Checks in Low Level TLB Handlers"
521 config ARC_UBOOT_SUPPORT
522 bool "Support uboot arg Handling"
525 ARC Linux by default checks for uboot provided args as pointers to
526 external cmdline or DTB. This however breaks in absence of uboot,
527 when booting from Metaware debugger directly, as the registers are
528 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
529 registers look like uboot args to kernel which then chokes.
530 So only enable the uboot arg checking/processing if users are sure
531 of uboot being in play.
533 config ARC_BUILTIN_DTB_NAME
534 string "Built in DTB"
536 Set the name of the DTB to embed in the vmlinux binary
537 Leaving it blank selects the minimal "skeleton" dtb
539 source "kernel/Kconfig.preempt"
541 menu "Executable file formats"
542 source "fs/Kconfig.binfmt"
545 endmenu # "ARC Architecture Configuration"
549 config FORCE_MAX_ZONEORDER
550 int "Maximum zone order"
551 default "12" if ARC_HUGEPAGE_16M
555 source "drivers/Kconfig"
560 bool "PCI support" if MIGHT_HAVE_PCI
562 PCI is the name of a bus system, i.e., the way the CPU talks to
563 the other stuff inside your box. Find out if your board/platform
566 Note: PCIe support for Synopsys Device will be available only
567 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
573 source "drivers/pci/Kconfig"
578 source "arch/arc/Kconfig.debug"
579 source "security/Kconfig"
580 source "crypto/Kconfig"
582 source "kernel/power/Kconfig"