1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/alpha/kernel/sys_alcor.c
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
9 * Code supporting the ALCOR and XLT (XL-300/366/433).
12 #include <linux/kernel.h>
13 #include <linux/types.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/reboot.h>
19 #include <linux/bitops.h>
21 #include <asm/ptrace.h>
24 #include <asm/mmu_context.h>
26 #include <asm/pgtable.h>
27 #include <asm/core_cia.h>
28 #include <asm/tlbflush.h>
33 #include "machvec_impl.h"
36 /* Note mask bit is true for ENABLED irqs. */
37 static unsigned long cached_irq_mask;
40 alcor_update_irq_hw(unsigned long mask)
42 *(vuip)GRU_INT_MASK = mask;
47 alcor_enable_irq(struct irq_data *d)
49 alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
53 alcor_disable_irq(struct irq_data *d)
55 alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
59 alcor_mask_and_ack_irq(struct irq_data *d)
63 /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
64 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
65 *(vuip)GRU_INT_CLEAR = 0; mb();
69 alcor_isa_mask_and_ack_irq(struct irq_data *d)
71 i8259a_mask_and_ack_irq(d);
73 /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
74 *(vuip)GRU_INT_CLEAR = 0x80000000; mb();
75 *(vuip)GRU_INT_CLEAR = 0; mb();
78 static struct irq_chip alcor_irq_type = {
80 .irq_unmask = alcor_enable_irq,
81 .irq_mask = alcor_disable_irq,
82 .irq_mask_ack = alcor_mask_and_ack_irq,
86 alcor_device_interrupt(unsigned long vector)
91 /* Read the interrupt summary register of the GRU */
92 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS;
95 * Now for every possible bit set, work through them and call
96 * the appropriate interrupt handler.
100 pld &= pld - 1; /* clear least bit set */
102 isa_device_interrupt(vector);
115 alpha_mv.device_interrupt = srm_device_interrupt;
117 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */
118 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */
119 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */
120 *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */
122 for (i = 16; i < 48; ++i) {
123 /* On Alcor, at least, lines 20..30 are not connected
124 and can generate spurious interrupts if we turn them
125 on while IRQ probing. */
126 if (i >= 16+20 && i <= 16+30)
128 irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
129 irq_set_status_flags(i, IRQ_LEVEL);
131 i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
134 common_init_isa_dma();
136 if (request_irq(16 + 31, no_action, 0, "isa-cascade", NULL))
137 pr_err("Failed to register isa-cascade interrupt\n");
142 * PCI Fixup configuration.
144 * Summary @ GRU_INT_REQ:
146 * 0 Interrupt Line A from slot 2
147 * 1 Interrupt Line B from slot 2
148 * 2 Interrupt Line C from slot 2
149 * 3 Interrupt Line D from slot 2
150 * 4 Interrupt Line A from slot 1
151 * 5 Interrupt line B from slot 1
152 * 6 Interrupt Line C from slot 1
153 * 7 Interrupt Line D from slot 1
154 * 8 Interrupt Line A from slot 0
155 * 9 Interrupt Line B from slot 0
156 *10 Interrupt Line C from slot 0
157 *11 Interrupt Line D from slot 0
158 *12 Interrupt Line A from slot 4
159 *13 Interrupt Line B from slot 4
160 *14 Interrupt Line C from slot 4
161 *15 Interrupt Line D from slot 4
162 *16 Interrupt Line D from slot 3
163 *17 Interrupt Line D from slot 3
164 *18 Interrupt Line D from slot 3
165 *19 Interrupt Line D from slot 3
169 * The device to slot mapping looks like:
172 * 6 built-in TULIP (XLT only)
173 * 7 PCI on board slot 0
174 * 8 PCI on board slot 3
175 * 9 PCI on board slot 4
176 * 10 PCEB (PCI-EISA bridge)
177 * 11 PCI on board slot 2
178 * 12 PCI on board slot 1
181 * This two layered interrupt approach means that we allocate IRQ 16 and
182 * above for PCI interrupts. The IRQ relates to which bit the interrupt
183 * comes in on. This makes interrupt processing much easier.
187 alcor_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
189 static char irq_tab[7][5] = {
190 /*INT INTA INTB INTC INTD */
191 /* note: IDSEL 17 is XLT only */
192 {16+13, 16+13, 16+13, 16+13, 16+13}, /* IdSel 17, TULIP */
193 { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 18, slot 0 */
194 {16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 19, slot 3 */
195 {16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 20, slot 4 */
196 { -1, -1, -1, -1, -1}, /* IdSel 21, PCEB */
197 { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 2 */
198 { 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
200 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
201 return COMMON_TABLE_LOOKUP;
205 alcor_kill_arch(int mode)
209 #ifndef ALPHA_RESTORE_SRM_SETUP
211 case LINUX_REBOOT_CMD_RESTART:
212 /* Who said DEC engineer's have no sense of humor? ;-) */
213 if (alpha_using_srm) {
214 *(vuip) GRU_RESET = 0x0000dead;
218 case LINUX_REBOOT_CMD_HALT:
220 case LINUX_REBOOT_CMD_POWER_OFF:
236 * Now we can look to see if we are really running on an XLT-type
237 * motherboard, by looking for a 21040 TULIP in slot 6, which is
238 * built into XLT and BRET/MAVERICK, but not available on ALCOR.
240 dev = pci_get_device(PCI_VENDOR_ID_DEC,
241 PCI_DEVICE_ID_DEC_TULIP,
243 if (dev && dev->devfn == PCI_DEVFN(6,0)) {
244 alpha_mv.sys.cia.gru_int_req_bits = XLT_GRU_INT_REQ_BITS;
245 printk(KERN_INFO "%s: Detected AS500 or XLT motherboard.\n",
256 struct alpha_machine_vector alcor_mv __initmv = {
257 .vector_name = "Alcor",
261 .machine_check = cia_machine_check,
262 .max_isa_dma_address = ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS,
263 .min_io_address = EISA_DEFAULT_IO_BASE,
264 .min_mem_address = CIA_DEFAULT_MEM_BASE,
267 .device_interrupt = alcor_device_interrupt,
269 .init_arch = cia_init_arch,
270 .init_irq = alcor_init_irq,
271 .init_rtc = common_init_rtc,
272 .init_pci = alcor_init_pci,
273 .kill_arch = alcor_kill_arch,
274 .pci_map_irq = alcor_map_irq,
275 .pci_swizzle = common_swizzle,
278 .gru_int_req_bits = ALCOR_GRU_INT_REQ_BITS
283 struct alpha_machine_vector xlt_mv __initmv = {
284 .vector_name = "XLT",
288 .machine_check = cia_machine_check,
289 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
290 .min_io_address = EISA_DEFAULT_IO_BASE,
291 .min_mem_address = CIA_DEFAULT_MEM_BASE,
294 .device_interrupt = alcor_device_interrupt,
296 .init_arch = cia_init_arch,
297 .init_irq = alcor_init_irq,
298 .init_rtc = common_init_rtc,
299 .init_pci = alcor_init_pci,
300 .kill_arch = alcor_kill_arch,
301 .pci_map_irq = alcor_map_irq,
302 .pci_swizzle = common_swizzle,
305 .gru_int_req_bits = XLT_GRU_INT_REQ_BITS
309 /* No alpha_mv alias for XLT, since we compile it in unconditionally
310 with ALCOR; setup_arch knows how to cope. */