1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/alpha/kernel/smp.c
5 * 2001-07-09 Phil Ezolt (Phillip.Ezolt@compaq.com)
6 * Renamed modified smp_call_function to smp_call_function_on_cpu()
7 * Created an function that conforms to the old calling convention
8 * of smp_call_function().
10 * This is helpful for DCPI.
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/sched/mm.h>
20 #include <linux/err.h>
21 #include <linux/threads.h>
22 #include <linux/smp.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/spinlock.h>
27 #include <linux/irq.h>
28 #include <linux/cache.h>
29 #include <linux/profile.h>
30 #include <linux/bitops.h>
31 #include <linux/cpu.h>
33 #include <asm/hwrpb.h>
34 #include <asm/ptrace.h>
35 #include <linux/atomic.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
48 #define DBGS(args) printk args
53 /* A collection of per-processor data. */
54 struct cpuinfo_alpha cpu_data[NR_CPUS];
55 EXPORT_SYMBOL(cpu_data);
57 /* A collection of single bit ipi messages. */
59 unsigned long bits ____cacheline_aligned;
60 } ipi_data[NR_CPUS] __cacheline_aligned;
62 enum ipi_message_type {
68 /* Set to a secondary's cpuid when it comes online. */
69 static int smp_secondary_alive = 0;
71 int smp_num_probed; /* Internal processor count */
72 int smp_num_cpus = 1; /* Number that came online. */
73 EXPORT_SYMBOL(smp_num_cpus);
76 * Called by both boot and secondaries to move global data into
77 * per-processor storage.
79 static inline void __init
80 smp_store_cpu_info(int cpuid)
82 cpu_data[cpuid].loops_per_jiffy = loops_per_jiffy;
83 cpu_data[cpuid].last_asn = ASN_FIRST_VERSION;
84 cpu_data[cpuid].need_new_asn = 0;
85 cpu_data[cpuid].asn_lock = 0;
89 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
91 static inline void __init
92 smp_setup_percpu_timer(int cpuid)
94 cpu_data[cpuid].prof_counter = 1;
95 cpu_data[cpuid].prof_multiplier = 1;
99 wait_boot_cpu_to_stop(int cpuid)
101 unsigned long stop = jiffies + 10*HZ;
103 while (time_before(jiffies, stop)) {
104 if (!smp_secondary_alive)
109 printk("wait_boot_cpu_to_stop: FAILED on CPU %d, hanging now\n", cpuid);
115 * Where secondaries begin a life of C.
120 int cpuid = hard_smp_processor_id();
122 if (cpu_online(cpuid)) {
123 printk("??, cpu 0x%x already present??\n", cpuid);
126 set_cpu_online(cpuid, true);
128 /* Turn on machine checks. */
131 /* Set trap vectors. */
134 /* Set interrupt vector. */
137 /* Get our local ticker going. */
138 smp_setup_percpu_timer(cpuid);
141 /* Call platform-specific callin, if specified */
142 if (alpha_mv.smp_callin)
143 alpha_mv.smp_callin();
145 /* All kernel threads share the same mm context. */
147 current->active_mm = &init_mm;
149 /* inform the notifiers about the new cpu */
150 notify_cpu_starting(cpuid);
152 /* Must have completely accurate bogos. */
155 /* Wait boot CPU to stop with irq enabled before running
157 wait_boot_cpu_to_stop(cpuid);
161 smp_store_cpu_info(cpuid);
162 /* Allow master to continue only after we written loops_per_jiffy. */
164 smp_secondary_alive = 1;
166 DBGS(("smp_callin: commencing CPU %d current %p active_mm %p\n",
167 cpuid, current, current->active_mm));
169 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
172 /* Wait until hwrpb->txrdy is clear for cpu. Return -1 on timeout. */
174 wait_for_txrdy (unsigned long cpumask)
176 unsigned long timeout;
178 if (!(hwrpb->txrdy & cpumask))
181 timeout = jiffies + 10*HZ;
182 while (time_before(jiffies, timeout)) {
183 if (!(hwrpb->txrdy & cpumask))
193 * Send a message to a secondary's console. "START" is one such
194 * interesting message. ;-)
197 send_secondary_console_msg(char *str, int cpuid)
199 struct percpu_struct *cpu;
200 register char *cp1, *cp2;
201 unsigned long cpumask;
204 cpu = (struct percpu_struct *)
206 + hwrpb->processor_offset
207 + cpuid * hwrpb->processor_size);
209 cpumask = (1UL << cpuid);
210 if (wait_for_txrdy(cpumask))
215 *(unsigned int *)&cpu->ipc_buffer[0] = len;
216 cp1 = (char *) &cpu->ipc_buffer[1];
217 memcpy(cp1, cp2, len);
219 /* atomic test and set */
221 set_bit(cpuid, &hwrpb->rxrdy);
223 if (wait_for_txrdy(cpumask))
228 printk("Processor %x not ready\n", cpuid);
232 * A secondary console wants to send a message. Receive it.
235 recv_secondary_console_msg(void)
238 unsigned long txrdy = hwrpb->txrdy;
239 char *cp1, *cp2, buf[80];
240 struct percpu_struct *cpu;
242 DBGS(("recv_secondary_console_msg: TXRDY 0x%lx.\n", txrdy));
244 mycpu = hard_smp_processor_id();
246 for (i = 0; i < NR_CPUS; i++) {
247 if (!(txrdy & (1UL << i)))
250 DBGS(("recv_secondary_console_msg: "
251 "TXRDY contains CPU %d.\n", i));
253 cpu = (struct percpu_struct *)
255 + hwrpb->processor_offset
256 + i * hwrpb->processor_size);
258 DBGS(("recv_secondary_console_msg: on %d from %d"
259 " HALT_REASON 0x%lx FLAGS 0x%lx\n",
260 mycpu, i, cpu->halt_reason, cpu->flags));
262 cnt = cpu->ipc_buffer[0] >> 32;
263 if (cnt <= 0 || cnt >= 80)
264 strcpy(buf, "<<< BOGUS MSG >>>");
266 cp1 = (char *) &cpu->ipc_buffer[1];
268 memcpy(cp2, cp1, cnt);
271 while ((cp2 = strchr(cp2, '\r')) != 0) {
278 DBGS((KERN_INFO "recv_secondary_console_msg: on %d "
279 "message is '%s'\n", mycpu, buf));
286 * Convince the console to have a secondary cpu begin execution.
289 secondary_cpu_start(int cpuid, struct task_struct *idle)
291 struct percpu_struct *cpu;
292 struct pcb_struct *hwpcb, *ipcb;
293 unsigned long timeout;
295 cpu = (struct percpu_struct *)
297 + hwrpb->processor_offset
298 + cpuid * hwrpb->processor_size);
299 hwpcb = (struct pcb_struct *) cpu->hwpcb;
300 ipcb = &task_thread_info(idle)->pcb;
302 /* Initialize the CPU's HWPCB to something just good enough for
303 us to get started. Immediately after starting, we'll swpctx
304 to the target idle task's pcb. Reuse the stack in the mean
305 time. Precalculate the target PCBB. */
306 hwpcb->ksp = (unsigned long)ipcb + sizeof(union thread_union) - 16;
308 hwpcb->ptbr = ipcb->ptbr;
311 hwpcb->unique = virt_to_phys(ipcb);
312 hwpcb->flags = ipcb->flags;
313 hwpcb->res1 = hwpcb->res2 = 0;
316 DBGS(("KSP 0x%lx PTBR 0x%lx VPTBR 0x%lx UNIQUE 0x%lx\n",
317 hwpcb->ksp, hwpcb->ptbr, hwrpb->vptb, hwpcb->unique));
319 DBGS(("Starting secondary cpu %d: state 0x%lx pal_flags 0x%lx\n",
320 cpuid, idle->state, ipcb->flags));
322 /* Setup HWRPB fields that SRM uses to activate secondary CPU */
323 hwrpb->CPU_restart = __smp_callin;
324 hwrpb->CPU_restart_data = (unsigned long) __smp_callin;
326 /* Recalculate and update the HWRPB checksum */
327 hwrpb_update_checksum(hwrpb);
330 * Send a "start" command to the specified processor.
333 /* SRM III 3.4.1.3 */
334 cpu->flags |= 0x22; /* turn on Context Valid and Restart Capable */
335 cpu->flags &= ~1; /* turn off Bootstrap In Progress */
338 send_secondary_console_msg("START\r\n", cpuid);
340 /* Wait 10 seconds for an ACK from the console. */
341 timeout = jiffies + 10*HZ;
342 while (time_before(jiffies, timeout)) {
348 printk(KERN_ERR "SMP: Processor %d failed to start.\n", cpuid);
352 DBGS(("secondary_cpu_start: SUCCESS for CPU %d!!!\n", cpuid));
357 * Bring one cpu online.
360 smp_boot_one_cpu(int cpuid, struct task_struct *idle)
362 unsigned long timeout;
364 /* Signal the secondary to wait a moment. */
365 smp_secondary_alive = -1;
367 /* Whirrr, whirrr, whirrrrrrrrr... */
368 if (secondary_cpu_start(cpuid, idle))
371 /* Notify the secondary CPU it can run calibrate_delay. */
373 smp_secondary_alive = 0;
375 /* We've been acked by the console; wait one second for
376 the task to start up for real. */
377 timeout = jiffies + 1*HZ;
378 while (time_before(jiffies, timeout)) {
379 if (smp_secondary_alive == 1)
385 /* We failed to boot the CPU. */
387 printk(KERN_ERR "SMP: Processor %d is stuck.\n", cpuid);
391 /* Another "Red Snapper". */
396 * Called from setup_arch. Detect an SMP system and which processors
402 struct percpu_struct *cpubase, *cpu;
405 if (boot_cpuid != 0) {
406 printk(KERN_WARNING "SMP: Booting off cpu %d instead of 0?\n",
410 if (hwrpb->nr_processors > 1) {
413 DBGS(("setup_smp: nr_processors %ld\n",
414 hwrpb->nr_processors));
416 cpubase = (struct percpu_struct *)
417 ((char*)hwrpb + hwrpb->processor_offset);
418 boot_cpu_palrev = cpubase->pal_revision;
420 for (i = 0; i < hwrpb->nr_processors; i++) {
421 cpu = (struct percpu_struct *)
422 ((char *)cpubase + i*hwrpb->processor_size);
423 if ((cpu->flags & 0x1cc) == 0x1cc) {
425 set_cpu_possible(i, true);
426 set_cpu_present(i, true);
427 cpu->pal_revision = boot_cpu_palrev;
430 DBGS(("setup_smp: CPU %d: flags 0x%lx type 0x%lx\n",
431 i, cpu->flags, cpu->type));
432 DBGS(("setup_smp: CPU %d: PAL rev 0x%lx\n",
433 i, cpu->pal_revision));
439 printk(KERN_INFO "SMP: %d CPUs probed -- cpu_present_mask = %lx\n",
440 smp_num_probed, cpumask_bits(cpu_present_mask)[0]);
444 * Called by smp_init prepare the secondaries
447 smp_prepare_cpus(unsigned int max_cpus)
449 /* Take care of some initial bookkeeping. */
450 memset(ipi_data, 0, sizeof(ipi_data));
452 current_thread_info()->cpu = boot_cpuid;
454 smp_store_cpu_info(boot_cpuid);
455 smp_setup_percpu_timer(boot_cpuid);
457 /* Nothing to do on a UP box, or when told not to. */
458 if (smp_num_probed == 1 || max_cpus == 0) {
459 init_cpu_possible(cpumask_of(boot_cpuid));
460 init_cpu_present(cpumask_of(boot_cpuid));
461 printk(KERN_INFO "SMP mode deactivated.\n");
465 printk(KERN_INFO "SMP starting up secondaries.\n");
467 smp_num_cpus = smp_num_probed;
471 smp_prepare_boot_cpu(void)
476 __cpu_up(unsigned int cpu, struct task_struct *tidle)
478 smp_boot_one_cpu(cpu, tidle);
480 return cpu_online(cpu) ? 0 : -ENOSYS;
484 smp_cpus_done(unsigned int max_cpus)
487 unsigned long bogosum = 0;
489 for(cpu = 0; cpu < NR_CPUS; cpu++)
491 bogosum += cpu_data[cpu].loops_per_jiffy;
493 printk(KERN_INFO "SMP: Total of %d processors activated "
494 "(%lu.%02lu BogoMIPS).\n",
496 (bogosum + 2500) / (500000/HZ),
497 ((bogosum + 2500) / (5000/HZ)) % 100);
501 setup_profiling_timer(unsigned int multiplier)
507 send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
512 for_each_cpu(i, to_whom)
513 set_bit(operation, &ipi_data[i].bits);
516 for_each_cpu(i, to_whom)
521 handle_ipi(struct pt_regs *regs)
523 int this_cpu = smp_processor_id();
524 unsigned long *pending_ipis = &ipi_data[this_cpu].bits;
528 DBGS(("handle_ipi: on CPU %d ops 0x%lx PC 0x%lx\n",
529 this_cpu, *pending_ipis, regs->pc));
532 mb(); /* Order interrupt and bit testing. */
533 while ((ops = xchg(pending_ipis, 0)) != 0) {
534 mb(); /* Order bit clearing and data access. */
540 which = __ffs(which);
548 generic_smp_call_function_interrupt();
555 printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n",
561 mb(); /* Order data access and bit testing. */
564 cpu_data[this_cpu].ipi_count++;
567 recv_secondary_console_msg();
571 smp_send_reschedule(int cpu)
574 if (cpu == hard_smp_processor_id())
576 "smp_send_reschedule: Sending IPI to self.\n");
578 send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
585 cpumask_copy(&to_whom, cpu_possible_mask);
586 cpumask_clear_cpu(smp_processor_id(), &to_whom);
588 if (hard_smp_processor_id() != boot_cpu_id)
589 printk(KERN_WARNING "smp_send_stop: Not on boot cpu.\n");
591 send_ipi_message(&to_whom, IPI_CPU_STOP);
594 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
596 send_ipi_message(mask, IPI_CALL_FUNC);
599 void arch_send_call_function_single_ipi(int cpu)
601 send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
605 ipi_imb(void *ignored)
613 /* Must wait other processors to flush their icache before continue. */
614 on_each_cpu(ipi_imb, NULL, 1);
616 EXPORT_SYMBOL(smp_imb);
619 ipi_flush_tlb_all(void *ignored)
627 /* Although we don't have any data to pass, we do want to
628 synchronize with the other processors. */
629 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
632 #define asn_locked() (cpu_data[smp_processor_id()].asn_lock)
635 ipi_flush_tlb_mm(void *x)
637 struct mm_struct *mm = (struct mm_struct *) x;
638 if (mm == current->active_mm && !asn_locked())
639 flush_tlb_current(mm);
645 flush_tlb_mm(struct mm_struct *mm)
649 if (mm == current->active_mm) {
650 flush_tlb_current(mm);
651 if (atomic_read(&mm->mm_users) <= 1) {
652 int cpu, this_cpu = smp_processor_id();
653 for (cpu = 0; cpu < NR_CPUS; cpu++) {
654 if (!cpu_online(cpu) || cpu == this_cpu)
656 if (mm->context[cpu])
657 mm->context[cpu] = 0;
664 smp_call_function(ipi_flush_tlb_mm, mm, 1);
668 EXPORT_SYMBOL(flush_tlb_mm);
670 struct flush_tlb_page_struct {
671 struct vm_area_struct *vma;
672 struct mm_struct *mm;
677 ipi_flush_tlb_page(void *x)
679 struct flush_tlb_page_struct *data = (struct flush_tlb_page_struct *)x;
680 struct mm_struct * mm = data->mm;
682 if (mm == current->active_mm && !asn_locked())
683 flush_tlb_current_page(mm, data->vma, data->addr);
689 flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
691 struct flush_tlb_page_struct data;
692 struct mm_struct *mm = vma->vm_mm;
696 if (mm == current->active_mm) {
697 flush_tlb_current_page(mm, vma, addr);
698 if (atomic_read(&mm->mm_users) <= 1) {
699 int cpu, this_cpu = smp_processor_id();
700 for (cpu = 0; cpu < NR_CPUS; cpu++) {
701 if (!cpu_online(cpu) || cpu == this_cpu)
703 if (mm->context[cpu])
704 mm->context[cpu] = 0;
715 smp_call_function(ipi_flush_tlb_page, &data, 1);
719 EXPORT_SYMBOL(flush_tlb_page);
722 flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
724 /* On the Alpha we always flush the whole user tlb. */
725 flush_tlb_mm(vma->vm_mm);
727 EXPORT_SYMBOL(flush_tlb_range);
730 ipi_flush_icache_page(void *x)
732 struct mm_struct *mm = (struct mm_struct *) x;
733 if (mm == current->active_mm && !asn_locked())
734 __load_new_mm_context(mm);
740 flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
741 unsigned long addr, int len)
743 struct mm_struct *mm = vma->vm_mm;
745 if ((vma->vm_flags & VM_EXEC) == 0)
750 if (mm == current->active_mm) {
751 __load_new_mm_context(mm);
752 if (atomic_read(&mm->mm_users) <= 1) {
753 int cpu, this_cpu = smp_processor_id();
754 for (cpu = 0; cpu < NR_CPUS; cpu++) {
755 if (!cpu_online(cpu) || cpu == this_cpu)
757 if (mm->context[cpu])
758 mm->context[cpu] = 0;
765 smp_call_function(ipi_flush_icache_page, mm, 1);