1 ==================================
2 DMAengine controller documentation
3 ==================================
8 Most of the Slave DMA controllers have the same general principles of
11 They have a given number of channels to use for the DMA transfers, and
12 a given number of requests lines.
14 Requests and channels are pretty much orthogonal. Channels can be used
15 to serve several to any requests. To simplify, channels are the
16 entities that will be doing the copy, and requests what endpoints are
19 The request lines actually correspond to physical lines going from the
20 DMA-eligible devices to the controller itself. Whenever the device
21 will want to start a transfer, it will assert a DMA request (DRQ) by
22 asserting that request line.
24 A very simple DMA controller would only take into account a single
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
29 That wouldn't work well in the real world, since slave devices might
30 require a specific number of bits to be transferred in a single
31 cycle. For example, we may want to transfer as much data as the
32 physical bus allows to maximize performances when doing a simple
33 memory copy operation, but our audio device could have a narrower FIFO
34 that requires data to be written exactly 16 or 24 bits at a time. This
35 is why most if not all of the DMA controllers can adjust this, using a
36 parameter called the transfer width.
38 Moreover, some DMA controllers, whenever the RAM is used as a source
39 or destination, can group the reads or writes in memory into a buffer,
40 so instead of having a lot of small memory accesses, which is not
41 really efficient, you'll get several bigger transfers. This is done
42 using a parameter called the burst size, that defines how many single
43 reads/writes it's allowed to do without the controller splitting the
44 transfer into smaller sub-transfers.
46 Our theoretical DMA controller would then only be able to do transfers
47 that involve a single contiguous block of data. However, some of the
48 transfers we usually have are not, and want to copy data from
49 non-contiguous buffers to a contiguous buffer, which is called
52 DMAEngine, at least for mem2dev transfers, require support for
53 scatter-gather. So we're left with two cases here: either we have a
54 quite simple DMA controller that doesn't support it, and we'll have to
55 implement it in software, or we have a more advanced DMA controller,
56 that implements in hardware scatter-gather.
58 The latter are usually programmed using a collection of chunks to
59 transfer, and whenever the transfer is started, the controller will go
60 over that collection, doing whatever we programmed there.
62 This collection is usually either a table or a linked list. You will
63 then push either the address of the table and its number of elements,
64 or the first item of the list to one channel of the DMA controller,
65 and whenever a DRQ will be asserted, it will go through the collection
66 to know where to fetch the data from.
68 Either way, the format of this collection is completely dependent on
69 your hardware. Each DMA controller will require a different structure,
70 but all of them will require, for every chunk, at least the source and
71 destination addresses, whether it should increment these addresses or
72 not and the three parameters we saw earlier: the burst size, the
73 transfer width and the transfer size.
75 The one last thing is that usually, slave devices won't issue DRQ by
76 default, and you have to enable this in your slave device driver first
77 whenever you're willing to use DMA.
79 These were just the general memory-to-memory (also called mem2mem) or
80 memory-to-device (mem2dev) kind of transfers. Most devices often
81 support other kind of transfers or memory operations that dmaengine
82 support and will be detailed later in this document.
87 Historically, DMA controller drivers have been implemented using the
88 async TX API, to offload operations such as memory copy, XOR,
89 cryptography, etc., basically any memory to memory operation.
91 Over time, the need for memory to device transfers arose, and
92 dmaengine was extended. Nowadays, the async TX API is written as a
93 layer on top of dmaengine, and acts as a client. Still, dmaengine
94 accommodates that API in some cases, and made some design choices to
95 ensure that it stayed compatible.
97 For more information on the Async TX API, please look the relevant
98 documentation file in Documentation/crypto/async-tx-api.rst.
103 ``struct dma_device`` Initialization
104 ------------------------------------
106 Just like any other kernel framework, the whole DMAEngine registration
107 relies on the driver filling a structure and registering against the
108 framework. In our case, that structure is dma_device.
110 The first thing you need to do in your driver is to allocate this
111 structure. Any of the usual memory allocators will do, but you'll also
112 need to initialize a few fields in there:
114 - ``channels``: should be initialized as a list using the
115 INIT_LIST_HEAD macro for example
117 - ``src_addr_widths``:
118 should contain a bitmask of the supported source transfer width
120 - ``dst_addr_widths``:
121 should contain a bitmask of the supported destination transfer width
124 should contain a bitmask of the supported slave directions
125 (i.e. excluding mem2mem transfers)
127 - ``residue_granularity``:
128 granularity of the transfer residue reported to dma_set_residue.
132 your device doesn't support any kind of residue
133 reporting. The framework will only know that a particular
134 transaction descriptor is done.
137 your device is able to report which chunks have been transferred
140 your device is able to report which burst have been transferred
142 - ``dev``: should hold the pointer to the ``struct device`` associated
143 to your current driver instance.
145 Supported transaction types
146 ---------------------------
148 The next thing you need is to set which transaction types your device
149 (and driver) supports.
151 Our ``dma_device structure`` has a field called cap_mask that holds the
152 various types of transaction supported, and you need to modify this
153 mask using the dma_cap_set function, with various flags depending on
154 transaction types you support as an argument.
156 All those capabilities are defined in the ``dma_transaction_type enum``,
157 in ``include/linux/dmaengine.h``
159 Currently, the types available are:
163 - The device is able to do memory to memory copies
167 - The device is able to perform XOR operations on memory areas
169 - Used to accelerate XOR intensive tasks, such as RAID5
173 - The device is able to perform parity check using the XOR
174 algorithm against a memory buffer.
178 - The device is able to perform RAID6 P+Q computations, P being a
179 simple XOR, and Q being a Reed-Solomon algorithm.
183 - The device is able to perform parity check using RAID6 P+Q
184 algorithm against a memory buffer.
188 - The device is able to trigger a dummy transfer that will
189 generate periodic interrupts
191 - Used by the client drivers to register a callback that will be
192 called on a regular basis through the DMA controller interrupt
196 - The devices only supports slave transfers, and as such isn't
197 available for async transfers.
201 - Must not be set by the device, and will be set by the framework
204 - TODO: What is it about?
208 - The device can handle device to memory transfers, including
209 scatter-gather transfers.
211 - While in the mem2mem case we were having two distinct types to
212 deal with a single chunk to copy or a collection of them, here,
213 we just have a single transaction type that is supposed to
216 - If you want to transfer a single contiguous memory buffer,
217 simply build a scatter list with only one item.
221 - The device can handle cyclic transfers.
223 - A cyclic transfer is a transfer where the chunk collection will
224 loop over itself, with the last item pointing to the first.
226 - It's usually used for audio transfers, where you want to operate
227 on a single ring buffer that you will fill with your audio data.
231 - The device supports interleaved transfer.
233 - These transfers can transfer data from a non-contiguous buffer
234 to a non-contiguous buffer, opposed to DMA_SLAVE that can
235 transfer data from a non-contiguous data set to a continuous
238 - It's usually used for 2d content transfers, in which case you
239 want to transfer a portion of uncompressed data directly to the
244 - The device supports repeated transfers. A repeated transfer, indicated by
245 the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that
246 it gets automatically repeated when it ends, but can additionally be
247 replaced by the client.
249 - This feature is limited to interleaved transfers, this flag should thus not
250 be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on
251 the current needs of DMA clients, support for additional transfer types
252 should be added in the future if and when the need arises.
256 - The device supports replacing repeated transfers at end of transfer (EOT)
257 by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.
259 - Support for replacing a currently running transfer at another point (such
260 as end of burst instead of end of transfer) will be added in the future
261 based on DMA clients needs, if and when the need arises.
263 These various types will also affect how the source and destination
264 addresses change over time.
266 Addresses pointing to RAM are typically incremented (or decremented)
267 after each transfer. In case of a ring buffer, they may loop
268 (DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO)
271 Per descriptor metadata support
272 -------------------------------
273 Some data movement architecture (DMA controller and peripherals) uses metadata
274 associated with a transaction. The DMA controller role is to transfer the
275 payload and the metadata alongside.
276 The metadata itself is not used by the DMA engine itself, but it contains
277 parameters, keys, vectors, etc for peripheral or from the peripheral.
279 The DMAengine framework provides a generic ways to facilitate the metadata for
280 descriptors. Depending on the architecture the DMA driver can implement either
281 or both of the methods and it is up to the client driver to choose which one
284 - DESC_METADATA_CLIENT
286 The metadata buffer is allocated/provided by the client driver and it is
287 attached (via the dmaengine_desc_attach_metadata() helper to the descriptor.
289 From the DMA driver the following is expected for this mode:
291 - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM
293 The data from the provided metadata buffer should be prepared for the DMA
294 controller to be sent alongside of the payload data. Either by copying to a
295 hardware descriptor, or highly coupled packet.
299 On transfer completion the DMA driver must copy the metadata to the client
300 provided metadata buffer before notifying the client about the completion.
301 After the transfer completion, DMA drivers must not touch the metadata
302 buffer provided by the client.
304 - DESC_METADATA_ENGINE
306 The metadata buffer is allocated/managed by the DMA driver. The client driver
307 can ask for the pointer, maximum size and the currently used size of the
308 metadata and can directly update or read it. dmaengine_desc_get_metadata_ptr()
309 and dmaengine_desc_set_metadata_len() is provided as helper functions.
311 From the DMA driver the following is expected for this mode:
315 Should return a pointer for the metadata buffer, the maximum size of the
316 metadata buffer and the currently used / valid (if any) bytes in the buffer.
320 It is called by the clients after it have placed the metadata to the buffer
321 to let the DMA driver know the number of valid bytes provided.
323 Note: since the client will ask for the metadata pointer in the completion
324 callback (in DMA_DEV_TO_MEM case) the DMA driver must ensure that the
325 descriptor is not freed up prior the callback is called.
330 Our dma_device structure also requires a few function pointers in
331 order to implement the actual logic, now that we described what
332 operations we were able to perform.
334 The functions that we have to fill in there, and hence have to
335 implement, obviously depend on the transaction types you reported as
338 - ``device_alloc_chan_resources``
340 - ``device_free_chan_resources``
342 - These functions will be called whenever a driver will call
343 ``dma_request_channel`` or ``dma_release_channel`` for the first/last
344 time on the channel associated to that driver.
346 - They are in charge of allocating/freeing all the needed
347 resources in order for that channel to be useful for your driver.
349 - These functions can sleep.
351 - ``device_prep_dma_*``
353 - These functions are matching the capabilities you registered
356 - These functions all take the buffer or the scatterlist relevant
357 for the transfer being prepared, and should create a hardware
358 descriptor or a list of hardware descriptors from it
360 - These functions can be called from an interrupt context
362 - Any allocation you might do should be using the GFP_NOWAIT
363 flag, in order not to potentially sleep, but without depleting
364 the emergency pool either.
366 - Drivers should try to pre-allocate any memory they might need
367 during the transfer setup at probe time to avoid putting to
368 much pressure on the nowait allocator.
370 - It should return a unique instance of the
371 ``dma_async_tx_descriptor structure``, that further represents this
374 - This structure can be initialized using the function
375 ``dma_async_tx_descriptor_init``.
377 - You'll also need to set two fields in this structure:
380 TODO: Can it be modified by the driver itself, or
381 should it be always the flags passed in the arguments
383 - tx_submit: A pointer to a function you have to implement,
384 that is supposed to push the current transaction descriptor to a
385 pending queue, waiting for issue_pending to be called.
387 - In this structure the function pointer callback_result can be
388 initialized in order for the submitter to be notified that a
389 transaction has completed. In the earlier code the function pointer
390 callback has been used. However it does not provide any status to the
391 transaction and will be deprecated. The result structure defined as
392 ``dmaengine_result`` that is passed in to callback_result
395 - result: This provides the transfer result defined by
396 ``dmaengine_tx_result``. Either success or some error condition.
398 - residue: Provides the residue bytes of the transfer for those that
401 - ``device_issue_pending``
403 - Takes the first transaction descriptor in the pending queue,
404 and starts the transfer. Whenever that transfer is done, it
405 should move to the next transaction in the list.
407 - This function can be called in an interrupt context
409 - ``device_tx_status``
411 - Should report the bytes left to go over on the given channel
413 - Should only care about the transaction descriptor passed as
414 argument, not the currently active one on a given channel
416 - The tx_state argument might be NULL
418 - Should use dma_set_residue to report it
420 - In the case of a cyclic transfer, it should only take into
421 account the current period.
423 - This function can be called in an interrupt context.
427 - Reconfigures the channel with the configuration given as argument
429 - This command should NOT perform synchronously, or on any
430 currently queued transfers, but only on subsequent ones
432 - In this case, the function will receive a ``dma_slave_config``
433 structure pointer as an argument, that will detail which
434 configuration to use.
436 - Even though that structure contains a direction field, this
437 field is deprecated in favor of the direction argument given to
440 - This call is mandatory for slave operations only. This should NOT be
441 set or expected to be set for memcpy operations.
442 If a driver support both, it should use this call for slave
443 operations only and not for memcpy ones.
447 - Pauses a transfer on the channel
449 - This command should operate synchronously on the channel,
450 pausing right away the work of the given channel
454 - Resumes a transfer on the channel
456 - This command should operate synchronously on the channel,
457 resuming right away the work of the given channel
459 - device_terminate_all
461 - Aborts all the pending and ongoing transfers on the channel
463 - For aborted transfers the complete callback should not be called
465 - Can be called from atomic context or from within a complete
466 callback of a descriptor. Must not sleep. Drivers must be able
467 to handle this correctly.
469 - Termination may be asynchronous. The driver does not have to
470 wait until the currently active transfer has completely stopped.
471 See device_synchronize.
475 - Must synchronize the termination of a channel to the current
478 - Must make sure that memory for previously submitted
479 descriptors is no longer accessed by the DMA controller.
481 - Must make sure that all complete callbacks for previously
482 submitted descriptors have finished running and none are
491 (stuff that should be documented, but don't really know
494 ``dma_run_dependencies``
496 - Should be called at the end of an async TX transfer, and can be
497 ignored in the slave transfers case.
499 - Makes sure that dependent operations are run before marking it
504 - it's a DMA transaction ID that will increment over time.
506 - Not really relevant any more since the introduction of ``virt-dma``
507 that abstracts it away.
511 - If clear, the descriptor cannot be reused by provider until the
512 client acknowledges receipt, i.e. has has a chance to establish any
515 - This can be acked by invoking async_tx_ack()
517 - If set, does not mean descriptor can be reused
521 - If set, the descriptor can be reused after being completed. It should
522 not be freed by provider if this flag is set.
524 - The descriptor should be prepared for reuse by invoking
525 ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE.
527 - ``dmaengine_desc_set_reuse()`` will succeed only when channel support
528 reusable descriptor as exhibited by capabilities
530 - As a consequence, if a device driver wants to skip the
531 ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers,
532 because the DMA'd data wasn't used, it can resubmit the transfer right after
535 - Descriptor can be freed in few ways
537 - Clearing DMA_CTRL_REUSE by invoking
538 ``dmaengine_desc_clear_reuse()`` and submitting for last txn
540 - Explicitly invoking ``dmaengine_desc_free()``, this can succeed only
541 when DMA_CTRL_REUSE is already set
543 - Terminating the channel
547 - If set, the client driver tells DMA controller that passed data in DMA
550 - Interpretation of command data is DMA controller specific. It can be
551 used for issuing commands to other peripherals/register reads/register
552 writes for which the descriptor should be in different format from
553 normal data descriptors.
557 - If set, the transfer will be automatically repeated when it ends until a
558 new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag.
559 If the next transfer to be queued on the channel does not have the
560 DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the
561 client terminates all transfers.
563 - This flag is only supported if the channel reports the DMA_REPEAT
568 - If set, the transfer will replace the transfer currently being executed at
569 the end of the transfer.
571 - This is the default behaviour for non-repeated transfers, specifying
572 DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.
574 - When using repeated transfers, DMA clients will usually need to set the
575 DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep
576 repeating the last repeated transfer and ignore the new transfers being
577 queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was
578 stuck on the previous transfer.
580 - This flag is only supported if the channel reports the DMA_LOAD_EOT
586 Most of the DMAEngine drivers you'll see are based on a similar design
587 that handles the end of transfer interrupts in the handler, but defer
588 most work to a tasklet, including the start of a new transfer whenever
589 the previous transfer ended.
591 This is a rather inefficient design though, because the inter-transfer
592 latency will be not only the interrupt latency, but also the
593 scheduling latency of the tasklet, which will leave the channel idle
594 in between, which will slow down the global transfer rate.
596 You should avoid this kind of practice, and instead of electing a new
597 transfer in your tasklet, move that part to the interrupt handler in
598 order to have a shorter idle window (that we can't really avoid
604 - Burst: A number of consecutive read or write operations that
605 can be queued to buffers before being flushed to memory.
607 - Chunk: A contiguous collection of bursts
609 - Transfer: A collection of chunks (be it contiguous or not)
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