Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
   8
   9 maintainers:
  10   - Roger Quadros <rogerq@ti.com>
  11
  12 properties:
  13   compatible:
  14     items:
  15       - const: ti,j721e-usb
  16
  17   reg:
  18     description: module registers
  19
  20   ranges: true
  21
  22   power-domains:
  23     description:
  24       PM domain provider node and an args specifier containing
  25       the USB device id value. See,
  26       Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
  27
  28   clocks:
  29     description: Clock phandles to usb2_refclk and lpm_clk
  30     minItems: 2
  31     maxItems: 2
  32
  33   clock-names:
  34     items:
  35       - const: ref
  36       - const: lpm
  37
  38   ti,usb2-only:
  39     description:
  40       If present, it restricts the controller to USB2.0 mode of
  41       operation. Must be present if USB3 PHY is not available
  42       for USB.
  43     type: boolean
  44
  45   ti,vbus-divider:
  46     description:
  47       Should be present if USB VBUS line is connected to the
  48       VBUS pin of the SoC via a 1/3 voltage divider.
  49     type: boolean
  50
  51   assigned-clocks:
  52     maxItems: 1
  53
  54   assigned-clock-parents:
  55     maxItems: 1
  56
  57   '#address-cells':
  58     const: 2
  59
  60   '#size-cells':
  61     const: 2
  62
  63   dma-coherent: true
  64
  65 patternProperties:
  66   "^usb@":
  67     type: object
  68
  69 required:
  70   - compatible
  71   - reg
  72   - power-domains
  73   - clocks
  74   - clock-names
  75
  76 additionalProperties: false
  77
  78 examples:
  79   - |
  80     #include <dt-bindings/soc/ti,sci_pm_domain.h>
  81     #include <dt-bindings/interrupt-controller/arm-gic.h>
  82
  83     bus {
  84         #address-cells = <2>;
  85         #size-cells = <2>;
  86
  87         cdns_usb@4104000 {
  88             compatible = "ti,j721e-usb";
  89             reg = <0x00 0x4104000 0x00 0x100>;
  90             power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
  91             clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
  92             clock-names = "ref", "lpm";
  93             assigned-clocks = <&k3_clks 288 15>;        /* USB2_REFCLK */
  94             assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
  95             #address-cells = <2>;
  96             #size-cells = <2>;
  97
  98             usb@6000000 {
  99                   compatible = "cdns,usb3";
 100                   reg = <0x00 0x6000000 0x00 0x10000>,
 101                         <0x00 0x6010000 0x00 0x10000>,
 102                         <0x00 0x6020000 0x00 0x10000>;
 103                   reg-names = "otg", "xhci", "dev";
 104                   interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,        /* irq.0 */
 105                                <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,       /* irq.6 */
 106                                <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;       /* otgirq.0 */
 107                   interrupt-names = "host",
 108                                     "peripheral",
 109                                     "otg";
 110                   maximum-speed = "super-speed";
 111                   dr_mode = "otg";
 112             };
 113         };
 114     };