1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller
10 - Felipe Balbi <balbi@kernel.org>
13 This is usually a subnode to DWC3 glue to which it is connected, but can also
14 be presented as a standalone DT node with an optional vendor-specific
36 - const: synopsys,dwc3
41 It's either a single common DWC3 interrupt (dwc_usb3) or individual
42 interrupts for the host, gadget and DRD modes.
52 enum: [host, peripheral, otg]
56 In general the core supports three types of clocks. bus_early is a
57 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
58 PHY is suspended. suspend clocks a small part of the USB3 core when
59 SS PHY in P3. But particular cases may differ from that having less
60 or more clock sources with another names.
65 - enum: [bus_early, ref, suspend]
71 - description: USB2/HS PHY
72 - description: USB3/SS PHY
77 - description: USB2/HS PHY
78 - description: USB3/SS PHY
89 snps,usb2-lpm-disable:
90 description: Indicate if we don't want to enable USB2 HW LPM
93 snps,usb3_lpm_capable:
94 description: Determines if platform is USB3 LPM capable
97 snps,dis-start-transfer-quirk:
99 When set, disable isoc START TRANSFER command failure SW work-around
100 for DWC_usb31 version 1.70a-ea06 and prior.
103 snps,disable_scramble_quirk:
105 True when SW should disable data scrambling. Only really useful for FPGA
109 snps,has-lpm-erratum:
110 description: True when DWC3 was configured with LPM Erratum enabled
113 snps,lpm-nyet-threshold:
114 description: LPM NYET threshold
115 $ref: /schemas/types.yaml#/definitions/uint8
117 snps,u2exit_lfps_quirk:
118 description: Set if we want to enable u2exit lfps quirk
121 snps,u2ss_inp3_quirk:
122 description: Set if we enable P3 OK for U2/SS Inactive quirk
125 snps,req_p1p2p3_quirk:
127 When set, the core will always request for P1/P2/P3 transition sequence.
130 snps,del_p1p2p3_quirk:
132 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
136 snps,del_phy_power_chg_quirk:
137 description: When set core will delay PHY power change from P0 to P1/P2/P3.
140 snps,lfps_filter_quirk:
141 description: When set core will filter LFPS reception.
144 snps,rx_detect_poll_quirk:
146 when set core will disable a 400us delay to start Polling LFPS after
150 snps,tx_de_emphasis_quirk:
151 description: When set core will set Tx de-emphasis value
156 The value driven to the PHY is controlled by the LTSSM during USB3
158 $ref: /schemas/types.yaml#/definitions/uint8
160 - 0 # -6dB de-emphasis
161 - 1 # -3.5dB de-emphasis
164 snps,dis_u3_susphy_quirk:
165 description: When set core will disable USB3 suspend phy
168 snps,dis_u2_susphy_quirk:
169 description: When set core will disable USB2 suspend phy
172 snps,dis_enblslpm_quirk:
174 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
178 snps,dis-u1-entry-quirk:
179 description: Set if link entering into U1 needs to be disabled
182 snps,dis-u2-entry-quirk:
183 description: Set if link entering into U2 needs to be disabled
186 snps,dis_rxdet_inp3_quirk:
188 When set core will disable receiver detection in PHY P3 power state.
191 snps,dis-u2-freeclk-exists-quirk:
193 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
194 PHY doesn't provide a free-running PHY clock.
197 snps,dis-del-phy-power-chg-quirk:
199 When set core will change PHY power from P0 to P1/P2/P3 without delay.
202 snps,dis-tx-ipgap-linecheck-quirk:
203 description: When set, disable u2mac linestate check during HS transmit
206 snps,parkmode-disable-ss-quirk:
208 When set, all SuperSpeed bus instances in park mode are disabled.
211 snps,dis_metastability_quirk:
213 When set, disable metastability workaround. CAUTION! Use only if you are
214 absolutely sure of it.
217 snps,dis-split-quirk:
219 When set, change the way URBs are handled by the driver. Needed to
220 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
223 snps,is-utmi-l1-suspend:
225 True when DWC3 asserts output signal utmi_l1_suspend_n, false when
226 asserts utmi_sleep_n.
230 description: HIRD threshold
231 $ref: /schemas/types.yaml#/definitions/uint8
233 snps,hsphy_interface:
235 High-Speed PHY interface selection between UTMI+ and ULPI when the
236 DWC_USB3_HSPHY_INTERFACE has value 3.
237 $ref: /schemas/types.yaml#/definitions/uint8
240 snps,quirk-frame-length-adjustment:
242 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
243 length adjustment when the fladj_30mhz_sdbnd signal is invalid or
245 $ref: /schemas/types.yaml#/definitions/uint32
249 snps,rx-thr-num-pkt-prd:
251 Periodic ESS RX packet threshold count (host mode only). Set this and
252 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
253 programming guide section 1.2.4) to enable periodic ESS RX threshold.
254 $ref: /schemas/types.yaml#/definitions/uint8
258 snps,rx-max-burst-prd:
260 Max periodic ESS RX burst size (host mode only). Set this and
261 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
262 programming guide section 1.2.4) to enable periodic ESS RX threshold.
263 $ref: /schemas/types.yaml#/definitions/uint8
267 snps,tx-thr-num-pkt-prd:
269 Periodic ESS TX packet threshold count (host mode only). Set this and
270 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
271 programming guide section 1.2.3) to enable periodic ESS TX threshold.
272 $ref: /schemas/types.yaml#/definitions/uint8
276 snps,tx-max-burst-prd:
278 Max periodic ESS TX burst size (host mode only). Set this and
279 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
280 programming guide section 1.2.3) to enable periodic ESS TX threshold.
281 $ref: /schemas/types.yaml#/definitions/uint8
286 description: Determines if the FIFO *has* to be reallocated
290 snps,incr-burst-type-adjustment:
292 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
293 burst type enable and INCRx type. A single value means INCRX burst mode
294 enabled. If more than one value specified, undefined length INCR burst
295 type will be enabled with burst lengths utilized up to the maximum
296 of the values passed in this property.
297 $ref: /schemas/types.yaml#/definitions/uint32-array
302 enum: [1, 4, 8, 16, 32, 64, 128, 256]
304 unevaluatedProperties: false
314 compatible = "snps,dwc3";
315 reg = <0x4a030000 0xcfff>;
316 interrupts = <0 92 4>;
317 usb-phy = <&usb2_phy>, <&usb3_phy>;
318 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
322 compatible = "snps,dwc3";
323 reg = <0x4a000000 0xcfff>;
324 interrupts = <0 92 4>;
325 clocks = <&clk 1>, <&clk 2>, <&clk 3>;
326 clock-names = "bus_early", "ref", "suspend";
327 phys = <&usb2_phy>, <&usb3_phy>;
328 phy-names = "usb2-phy", "usb3-phy";
329 snps,dis_u2_susphy_quirk;
330 snps,dis_enblslpm_quirk;