1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller
10 - Felipe Balbi <balbi@kernel.org>
13 This is usually a subnode to DWC3 glue to which it is connected, but can also
14 be presented as a standalone DT node with an optional vendor-specific
36 - const: synopsys,dwc3
44 It's either a single common DWC3 interrupt (dwc_usb3) or individual
45 interrupts for the host, gadget and DRD modes.
55 enum: [host, peripheral, otg, wakeup]
59 In general the core supports three types of clocks. bus_early is a
60 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
61 PHY is suspended. suspend clocks a small part of the USB3 core when
62 SS PHY in P3. But particular cases may differ from that having less
63 or more clock sources with another names.
68 - enum: [bus_early, ref, suspend]
83 - description: USB2/HS PHY
84 - description: USB3/SS PHY
100 The DWC3 has 2 power-domains. The power management unit (PMU) and
101 everything else. The PMU is typically always powered and may not have an
106 - description: Power management unit
111 snps,usb2-lpm-disable:
112 description: Indicate if we don't want to enable USB2 HW LPM for host
116 snps,usb3_lpm_capable:
117 description: Determines if platform is USB3 LPM capable
120 snps,usb2-gadget-lpm-disable:
121 description: Indicate if we don't want to enable USB2 HW LPM for gadget
125 snps,dis-start-transfer-quirk:
127 When set, disable isoc START TRANSFER command failure SW work-around
128 for DWC_usb31 version 1.70a-ea06 and prior.
131 snps,disable_scramble_quirk:
133 True when SW should disable data scrambling. Only really useful for FPGA
137 snps,has-lpm-erratum:
138 description: True when DWC3 was configured with LPM Erratum enabled
141 snps,lpm-nyet-threshold:
142 description: LPM NYET threshold
143 $ref: /schemas/types.yaml#/definitions/uint8
145 snps,u2exit_lfps_quirk:
146 description: Set if we want to enable u2exit lfps quirk
149 snps,u2ss_inp3_quirk:
150 description: Set if we enable P3 OK for U2/SS Inactive quirk
153 snps,req_p1p2p3_quirk:
155 When set, the core will always request for P1/P2/P3 transition sequence.
158 snps,del_p1p2p3_quirk:
160 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
164 snps,del_phy_power_chg_quirk:
165 description: When set core will delay PHY power change from P0 to P1/P2/P3.
168 snps,lfps_filter_quirk:
169 description: When set core will filter LFPS reception.
172 snps,rx_detect_poll_quirk:
174 when set core will disable a 400us delay to start Polling LFPS after
178 snps,tx_de_emphasis_quirk:
179 description: When set core will set Tx de-emphasis value
184 The value driven to the PHY is controlled by the LTSSM during USB3
186 $ref: /schemas/types.yaml#/definitions/uint8
188 - 0 # -6dB de-emphasis
189 - 1 # -3.5dB de-emphasis
192 snps,dis_u3_susphy_quirk:
193 description: When set core will disable USB3 suspend phy
196 snps,dis_u2_susphy_quirk:
197 description: When set core will disable USB2 suspend phy
200 snps,dis_enblslpm_quirk:
202 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
206 snps,dis-u1-entry-quirk:
207 description: Set if link entering into U1 needs to be disabled
210 snps,dis-u2-entry-quirk:
211 description: Set if link entering into U2 needs to be disabled
214 snps,dis_rxdet_inp3_quirk:
216 When set core will disable receiver detection in PHY P3 power state.
219 snps,dis-u2-freeclk-exists-quirk:
221 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
222 PHY doesn't provide a free-running PHY clock.
225 snps,dis-del-phy-power-chg-quirk:
227 When set core will change PHY power from P0 to P1/P2/P3 without delay.
230 snps,dis-tx-ipgap-linecheck-quirk:
231 description: When set, disable u2mac linestate check during HS transmit
234 snps,parkmode-disable-ss-quirk:
236 When set, all SuperSpeed bus instances in park mode are disabled.
239 snps,parkmode-disable-hs-quirk:
241 When set, all HighSpeed bus instances in park mode are disabled.
244 snps,dis_metastability_quirk:
246 When set, disable metastability workaround. CAUTION! Use only if you are
247 absolutely sure of it.
250 snps,dis-split-quirk:
252 When set, change the way URBs are handled by the driver. Needed to
253 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
256 snps,gfladj-refclk-lpm-sel-quirk:
258 When set, run the SOF/ITP counter based on ref_clk.
261 snps,resume-hs-terminations:
263 Fix the issue of HS terminations CRC error on resume by enabling this
264 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
265 of resume. This option is to support certain legacy ULPI PHYs.
268 snps,ulpi-ext-vbus-drv:
270 Some ULPI USB PHY does not support internal VBUS supply, and driving
271 the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
272 bit. When set, the xhci host will configure the USB2 PHY drives VBUS
273 with an external supply.
276 snps,is-utmi-l1-suspend:
278 True when DWC3 asserts output signal utmi_l1_suspend_n, false when
279 asserts utmi_sleep_n.
283 description: HIRD threshold
284 $ref: /schemas/types.yaml#/definitions/uint8
286 snps,hsphy_interface:
288 High-Speed PHY interface selection between UTMI+ and ULPI when the
289 DWC_USB3_HSPHY_INTERFACE has value 3.
290 $ref: /schemas/types.yaml#/definitions/string
293 snps,quirk-frame-length-adjustment:
295 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
296 length adjustment when the fladj_30mhz_sdbnd signal is invalid or
298 $ref: /schemas/types.yaml#/definitions/uint32
302 snps,ref-clock-period-ns:
304 Value for REFCLKPER field of GUCTL register for reference clock period in
305 nanoseconds, when the hardware set default does not match the actual
308 This binding is deprecated. Instead, provide an appropriate reference clock.
315 USB RX packet threshold count. In host mode, this field specifies
316 the space that must be available in the RX FIFO before the core can
317 start the corresponding USB RX transaction (burst).
318 In device mode, this field specifies the space that must be
319 available in the RX FIFO before the core can send ERDY for a
320 flow-controlled endpoint. It is only used for SuperSpeed.
321 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
322 USB 3.0 Controller Databook)
323 $ref: /schemas/types.yaml#/definitions/uint8
329 Max USB RX burst size. In host mode, this field specifies the
330 Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
331 bus is slower than the USB, RX FIFO can overrun during a long burst.
332 You can program a smaller value to this field to limit the RX burst
333 size that the core can perform. It only applies to SS Bulk,
334 Isochronous, and Interrupt IN endpoints in the host mode.
335 In device mode, this field specifies the NUMP value that is sent in
336 ERDY for an OUT endpoint.
337 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
338 USB 3.0 Controller Databook)
339 $ref: /schemas/types.yaml#/definitions/uint8
345 USB TX packet threshold count. This field specifies the number of
346 packets that must be in the TXFIFO before the core can start
347 transmission for the corresponding USB transaction (burst).
348 This count is valid in both host and device modes. It is only used
349 for SuperSpeed operation.
350 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
352 $ref: /schemas/types.yaml#/definitions/uint8
358 Max USB TX burst size. When the system bus is slower than the USB,
359 TX FIFO can underrun during a long burst. Program a smaller value
360 to this field to limit the TX burst size that the core can execute.
361 In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
362 OUT endpoints. This value is not used in device mode.
363 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
365 $ref: /schemas/types.yaml#/definitions/uint8
369 snps,rx-thr-num-pkt-prd:
371 Periodic ESS RX packet threshold count (host mode only). Set this and
372 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
373 programming guide section 1.2.4) to enable periodic ESS RX threshold.
374 $ref: /schemas/types.yaml#/definitions/uint8
378 snps,rx-max-burst-prd:
380 Max periodic ESS RX burst size (host mode only). Set this and
381 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
382 programming guide section 1.2.4) to enable periodic ESS RX threshold.
383 $ref: /schemas/types.yaml#/definitions/uint8
387 snps,tx-thr-num-pkt-prd:
389 Periodic ESS TX packet threshold count (host mode only). Set this and
390 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
391 programming guide section 1.2.3) to enable periodic ESS TX threshold.
392 $ref: /schemas/types.yaml#/definitions/uint8
396 snps,tx-max-burst-prd:
398 Max periodic ESS TX burst size (host mode only). Set this and
399 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
400 programming guide section 1.2.3) to enable periodic ESS TX threshold.
401 $ref: /schemas/types.yaml#/definitions/uint8
406 description: Determines if the TX fifos can be dynamically resized depending
407 on the number of IN endpoints used and if bursting is supported. This
408 may help improve bandwidth on platforms with higher system latencies, as
409 increased fifo space allows for the controller to prefetch data into its
414 description: Specifies the max number of packets the txfifo resizing logic
415 can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
416 higher the number, the more fifo space the txfifo resizing logic will
417 allocate for that endpoint.
418 $ref: /schemas/types.yaml#/definitions/uint8
421 snps,incr-burst-type-adjustment:
423 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
424 burst type enable and INCRx type. A single value means INCRX burst mode
425 enabled. If more than one value specified, undefined length INCR burst
426 type will be enabled with burst lengths utilized up to the maximum
427 of the values passed in this property.
428 $ref: /schemas/types.yaml#/definitions/uint32-array
433 enum: [1, 4, 8, 16, 32, 64, 128, 256]
436 $ref: /schemas/graph.yaml#/properties/port
438 This port is used with the 'usb-role-switch' property to connect the
439 dwc3 to type C connector.
442 $ref: /schemas/graph.yaml#/properties/ports
444 Those ports should be used with any connector to the data bus of this
445 controller using the OF graph bindings specified if the "usb-role-switch"
450 $ref: /schemas/graph.yaml#/properties/port
451 description: High Speed (HS) data bus.
454 $ref: /schemas/graph.yaml#/properties/port
455 description: Super Speed (SS) data bus.
458 $ref: /schemas/types.yaml#/definitions/flag
460 Enable USB remote wakeup.
462 unevaluatedProperties: false
472 compatible = "snps,dwc3";
473 reg = <0x4a030000 0xcfff>;
474 interrupts = <0 92 4>;
475 usb-phy = <&usb2_phy>, <&usb3_phy>;
476 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
480 compatible = "snps,dwc3";
481 reg = <0x4a000000 0xcfff>;
482 interrupts = <0 92 4>;
483 clocks = <&clk 1>, <&clk 2>, <&clk 3>;
484 clock-names = "bus_early", "ref", "suspend";
485 phys = <&usb2_phy>, <&usb3_phy>;
486 phy-names = "usb2-phy", "usb3-phy";
487 snps,dis_u2_susphy_quirk;
488 snps,dis_enblslpm_quirk;