1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller
10 - Felipe Balbi <balbi@kernel.org>
13 This is usually a subnode to DWC3 glue to which it is connected, but can also
14 be presented as a standalone DT node with an optional vendor-specific
35 - const: fsl,imx8mq-dwc3
38 - const: synopsys,dwc3
46 It's either a single common DWC3 interrupt (dwc_usb3) or individual
47 interrupts for the host, gadget and DRD modes.
57 enum: [host, peripheral, otg]
61 In general the core supports three types of clocks. bus_early is a
62 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
63 PHY is suspended. suspend clocks a small part of the USB3 core when
64 SS PHY in P3. But particular cases may differ from that having less
65 or more clock sources with another names.
70 - enum: [bus_early, ref, suspend]
85 - description: USB2/HS PHY
86 - description: USB3/SS PHY
102 The DWC3 has 2 power-domains. The power management unit (PMU) and
103 everything else. The PMU is typically always powered and may not have an
108 - description: Power management unit
113 snps,usb2-lpm-disable:
114 description: Indicate if we don't want to enable USB2 HW LPM for host
118 snps,usb3_lpm_capable:
119 description: Determines if platform is USB3 LPM capable
122 snps,usb2-gadget-lpm-disable:
123 description: Indicate if we don't want to enable USB2 HW LPM for gadget
127 snps,dis-start-transfer-quirk:
129 When set, disable isoc START TRANSFER command failure SW work-around
130 for DWC_usb31 version 1.70a-ea06 and prior.
133 snps,disable_scramble_quirk:
135 True when SW should disable data scrambling. Only really useful for FPGA
139 snps,has-lpm-erratum:
140 description: True when DWC3 was configured with LPM Erratum enabled
143 snps,lpm-nyet-threshold:
144 description: LPM NYET threshold
145 $ref: /schemas/types.yaml#/definitions/uint8
147 snps,u2exit_lfps_quirk:
148 description: Set if we want to enable u2exit lfps quirk
151 snps,u2ss_inp3_quirk:
152 description: Set if we enable P3 OK for U2/SS Inactive quirk
155 snps,req_p1p2p3_quirk:
157 When set, the core will always request for P1/P2/P3 transition sequence.
160 snps,del_p1p2p3_quirk:
162 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
166 snps,del_phy_power_chg_quirk:
167 description: When set core will delay PHY power change from P0 to P1/P2/P3.
170 snps,lfps_filter_quirk:
171 description: When set core will filter LFPS reception.
174 snps,rx_detect_poll_quirk:
176 when set core will disable a 400us delay to start Polling LFPS after
180 snps,tx_de_emphasis_quirk:
181 description: When set core will set Tx de-emphasis value
186 The value driven to the PHY is controlled by the LTSSM during USB3
188 $ref: /schemas/types.yaml#/definitions/uint8
190 - 0 # -6dB de-emphasis
191 - 1 # -3.5dB de-emphasis
194 snps,dis_u3_susphy_quirk:
195 description: When set core will disable USB3 suspend phy
198 snps,dis_u2_susphy_quirk:
199 description: When set core will disable USB2 suspend phy
202 snps,dis_enblslpm_quirk:
204 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
208 snps,dis-u1-entry-quirk:
209 description: Set if link entering into U1 needs to be disabled
212 snps,dis-u2-entry-quirk:
213 description: Set if link entering into U2 needs to be disabled
216 snps,dis_rxdet_inp3_quirk:
218 When set core will disable receiver detection in PHY P3 power state.
221 snps,dis-u2-freeclk-exists-quirk:
223 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
224 PHY doesn't provide a free-running PHY clock.
227 snps,dis-del-phy-power-chg-quirk:
229 When set core will change PHY power from P0 to P1/P2/P3 without delay.
232 snps,dis-tx-ipgap-linecheck-quirk:
233 description: When set, disable u2mac linestate check during HS transmit
236 snps,parkmode-disable-ss-quirk:
238 When set, all SuperSpeed bus instances in park mode are disabled.
241 snps,dis_metastability_quirk:
243 When set, disable metastability workaround. CAUTION! Use only if you are
244 absolutely sure of it.
247 snps,dis-split-quirk:
249 When set, change the way URBs are handled by the driver. Needed to
250 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
253 snps,gfladj-refclk-lpm-sel-quirk:
255 When set, run the SOF/ITP counter based on ref_clk.
258 snps,resume-hs-terminations:
260 Fix the issue of HS terminations CRC error on resume by enabling this
261 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
262 of resume. This option is to support certain legacy ULPI PHYs.
265 snps,ulpi-ext-vbus-drv:
267 Some ULPI USB PHY does not support internal VBUS supply, and driving
268 the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
269 bit. When set, the xhci host will configure the USB2 PHY drives VBUS
270 with an external supply.
273 snps,is-utmi-l1-suspend:
275 True when DWC3 asserts output signal utmi_l1_suspend_n, false when
276 asserts utmi_sleep_n.
280 description: HIRD threshold
281 $ref: /schemas/types.yaml#/definitions/uint8
283 snps,hsphy_interface:
285 High-Speed PHY interface selection between UTMI+ and ULPI when the
286 DWC_USB3_HSPHY_INTERFACE has value 3.
287 $ref: /schemas/types.yaml#/definitions/uint8
290 snps,quirk-frame-length-adjustment:
292 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
293 length adjustment when the fladj_30mhz_sdbnd signal is invalid or
295 $ref: /schemas/types.yaml#/definitions/uint32
299 snps,ref-clock-period-ns:
301 Value for REFCLKPER field of GUCTL register for reference clock period in
302 nanoseconds, when the hardware set default does not match the actual
305 This binding is deprecated. Instead, provide an appropriate reference clock.
310 snps,rx-thr-num-pkt-prd:
312 Periodic ESS RX packet threshold count (host mode only). Set this and
313 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
314 programming guide section 1.2.4) to enable periodic ESS RX threshold.
315 $ref: /schemas/types.yaml#/definitions/uint8
319 snps,rx-max-burst-prd:
321 Max periodic ESS RX burst size (host mode only). Set this and
322 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
323 programming guide section 1.2.4) to enable periodic ESS RX threshold.
324 $ref: /schemas/types.yaml#/definitions/uint8
328 snps,tx-thr-num-pkt-prd:
330 Periodic ESS TX packet threshold count (host mode only). Set this and
331 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
332 programming guide section 1.2.3) to enable periodic ESS TX threshold.
333 $ref: /schemas/types.yaml#/definitions/uint8
337 snps,tx-max-burst-prd:
339 Max periodic ESS TX burst size (host mode only). Set this and
340 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
341 programming guide section 1.2.3) to enable periodic ESS TX threshold.
342 $ref: /schemas/types.yaml#/definitions/uint8
347 description: Determines if the TX fifos can be dynamically resized depending
348 on the number of IN endpoints used and if bursting is supported. This
349 may help improve bandwidth on platforms with higher system latencies, as
350 increased fifo space allows for the controller to prefetch data into its
355 description: Specifies the max number of packets the txfifo resizing logic
356 can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
357 higher the number, the more fifo space the txfifo resizing logic will
358 allocate for that endpoint.
359 $ref: /schemas/types.yaml#/definitions/uint8
362 snps,incr-burst-type-adjustment:
364 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
365 burst type enable and INCRx type. A single value means INCRX burst mode
366 enabled. If more than one value specified, undefined length INCR burst
367 type will be enabled with burst lengths utilized up to the maximum
368 of the values passed in this property.
369 $ref: /schemas/types.yaml#/definitions/uint32-array
374 enum: [1, 4, 8, 16, 32, 64, 128, 256]
377 $ref: /schemas/graph.yaml#/properties/port
379 This port is used with the 'usb-role-switch' property to connect the
380 dwc3 to type C connector.
383 $ref: /schemas/types.yaml#/definitions/flag
385 Enable USB remote wakeup.
387 unevaluatedProperties: false
397 compatible = "snps,dwc3";
398 reg = <0x4a030000 0xcfff>;
399 interrupts = <0 92 4>;
400 usb-phy = <&usb2_phy>, <&usb3_phy>;
401 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
405 compatible = "snps,dwc3";
406 reg = <0x4a000000 0xcfff>;
407 interrupts = <0 92 4>;
408 clocks = <&clk 1>, <&clk 2>, <&clk 3>;
409 clock-names = "bus_early", "ref", "suspend";
410 phys = <&usb2_phy>, <&usb3_phy>;
411 phy-names = "usb2-phy", "usb3-phy";
412 snps,dis_u2_susphy_quirk;
413 snps,dis_enblslpm_quirk;