1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Manu Gautam <mgautam@codeaurora.org>
28 description: Offset and length of register set for QSCRATCH wrapper
40 description: specifies a phandle to PM domain provider node
45 A list of phandle and clock-specifier pairs for the clocks
46 listed in clock-names.
48 - description: System Config NOC clock.
49 - description: Master/Core clock, has to be >= 125 MHz
50 for SS operation and >= 60MHz for HS operation.
51 - description: System bus AXI clock.
52 - description: Mock utmi clock needed for ITP/SOF generation
53 in host mode. Its frequency should be 19.2MHz.
54 - description: Sleep clock, used for wakeup when
55 USB3 core goes into low power mode (U3).
67 - description: Phandle and clock specifier of MOCK_UTMI_CLK.
68 - description: Phandle and clock specifoer of MASTER_CLK.
72 - description: Must be 19.2MHz (19200000).
73 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
87 - description: The interrupt that is asserted
88 when a wakeup event is received on USB2 bus.
89 - description: The interrupt that is asserted
90 when a wakeup event is received on USB3 bus.
91 - description: Wakeup event on DM line.
92 - description: Wakeup event on DP line.
98 - const: dm_hs_phy_irq
99 - const: dp_hs_phy_irq
101 qcom,select-utmi-as-pipe-clk:
103 If present, disable USB3 pipe_clk requirement.
104 Used when dwc3 operates without SSPHY and only
105 HS/FS/LS modes are supported.
108 # Required child node:
112 $ref: snps,dwc3.yaml#
126 additionalProperties: false
130 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
131 #include <dt-bindings/interrupt-controller/arm-gic.h>
132 #include <dt-bindings/interrupt-controller/irq.h>
134 #address-cells = <2>;
138 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
139 reg = <0 0x0a6f8800 0 0x400>;
141 #address-cells = <2>;
144 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
145 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
146 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
147 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
148 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
149 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
152 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
153 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
154 assigned-clock-rates = <19200000>, <150000000>;
156 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-names = "hs_phy_irq", "ss_phy_irq",
161 "dm_hs_phy_irq", "dp_hs_phy_irq";
163 power-domains = <&gcc USB30_PRIM_GDSC>;
165 resets = <&gcc GCC_USB30_PRIM_BCR>;
168 compatible = "snps,dwc3";
169 reg = <0 0x0a600000 0 0xcd00>;
170 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
171 iommus = <&apps_smmu 0x740 0>;
172 snps,dis_u2_susphy_quirk;
173 snps,dis_enblslpm_quirk;
174 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
175 phy-names = "usb2-phy", "usb3-phy";