1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Manu Gautam <mgautam@codeaurora.org>
31 description: Offset and length of register set for QSCRATCH wrapper
43 description: specifies a phandle to PM domain provider node
48 A list of phandle and clock-specifier pairs for the clocks
49 listed in clock-names.
51 - description: System Config NOC clock.
52 - description: Master/Core clock, has to be >= 125 MHz
53 for SS operation and >= 60MHz for HS operation.
54 - description: System bus AXI clock.
55 - description: Mock utmi clock needed for ITP/SOF generation
56 in host mode. Its frequency should be 19.2MHz.
57 - description: Sleep clock, used for wakeup when
58 USB3 core goes into low power mode (U3).
70 - description: Phandle and clock specifier of MOCK_UTMI_CLK.
71 - description: Phandle and clock specifoer of MASTER_CLK.
75 - description: Must be 19.2MHz (19200000).
76 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
90 - description: The interrupt that is asserted
91 when a wakeup event is received on USB2 bus.
92 - description: The interrupt that is asserted
93 when a wakeup event is received on USB3 bus.
94 - description: Wakeup event on DM line.
95 - description: Wakeup event on DP line.
101 - const: dm_hs_phy_irq
102 - const: dp_hs_phy_irq
104 qcom,select-utmi-as-pipe-clk:
106 If present, disable USB3 pipe_clk requirement.
107 Used when dwc3 operates without SSPHY and only
108 HS/FS/LS modes are supported.
111 # Required child node:
115 $ref: snps,dwc3.yaml#
129 additionalProperties: false
133 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
134 #include <dt-bindings/interrupt-controller/arm-gic.h>
135 #include <dt-bindings/interrupt-controller/irq.h>
137 #address-cells = <2>;
141 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
142 reg = <0 0x0a6f8800 0 0x400>;
144 #address-cells = <2>;
147 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
148 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
149 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
150 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
151 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
152 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
155 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
156 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
157 assigned-clock-rates = <19200000>, <150000000>;
159 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-names = "hs_phy_irq", "ss_phy_irq",
164 "dm_hs_phy_irq", "dp_hs_phy_irq";
166 power-domains = <&gcc USB30_PRIM_GDSC>;
168 resets = <&gcc GCC_USB30_PRIM_BCR>;
171 compatible = "snps,dwc3";
172 reg = <0 0x0a600000 0 0xcd00>;
173 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
174 iommus = <&apps_smmu 0x740 0>;
175 snps,dis_u2_susphy_quirk;
176 snps,dis_enblslpm_quirk;
177 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
178 phy-names = "usb2-phy", "usb3-phy";