1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: "usb-xhci.yaml"
17 There are two scenarios:
18 case 1: only supports xHCI driver;
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
22 # common properties for both case 1 and case 2
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
28 - mediatek,mt7622-xhci
29 - mediatek,mt7623-xhci
30 - mediatek,mt7629-xhci
31 - mediatek,mt8173-xhci
32 - mediatek,mt8183-xhci
33 - const: mediatek,mtk-xhci
38 - description: the registers of xHCI MAC
39 - description: the registers of IP Port Control
45 - const: ippc # optional, only needed for case 1.
51 description: A phandle to USB power domain node to control USB's MTCMOS
57 - description: Controller clock used by normal mode
58 - description: Reference clock used by low power mode etc
59 - description: Mcu bus clock for register access
60 - description: DMA bus clock for data transfer
61 - description: controller clock
66 - const: sys_ck # required, the following ones are optional
76 assigned-clock-parents:
82 List of all PHYs used on this HCD, it's better to keep PHYs in order
83 as the hardware layout
86 - description: USB2/HS PHY # required, others are optional
87 - description: USB3/SS(P) PHY
88 - description: USB2/HS PHY
89 - description: USB3/SS(P) PHY
90 - description: USB2/HS PHY
91 - description: USB3/SS(P) PHY
92 - description: USB2/HS PHY
93 - description: USB3/SS(P) PHY
94 - description: USB2/HS PHY
97 description: Regulator of USB AVDD3.3v
100 description: Regulator of USB VBUS5v
103 description: supports USB3.0 LPM
108 Interrupt moderation interval value, it is 8 times as much as that
109 defined in the xHCI spec on MTK's controller.
112 # the following properties are only used for case 1
114 description: enable USB remote wakeup, see power/wakeup-source.txt
117 mediatek,syscon-wakeup:
118 $ref: /schemas/types.yaml#/definitions/phandle-array
121 A phandle to syscon used to access the register of the USB wakeup glue
122 layer between xHCI and SPM, the field should always be 3 cells long.
126 The first cell represents a phandle to syscon
128 The second cell represents the register base address of the glue
131 The third cell represents the hardware version of the glue layer,
132 1 is used by mt8173 etc, 2 is used by mt2712 etc
135 mediatek,u3p-dis-msk:
136 $ref: /schemas/types.yaml#/definitions/uint32
137 description: The mask to disable u3ports, bit0 for u3port0,
138 bit1 for u3port1, ... etc
149 description: The hard wired USB devices.
152 wakeup-source: [ 'mediatek,syscon-wakeup' ]
162 additionalProperties: false
166 #include <dt-bindings/clock/mt8173-clk.h>
167 #include <dt-bindings/interrupt-controller/arm-gic.h>
168 #include <dt-bindings/interrupt-controller/irq.h>
169 #include <dt-bindings/phy/phy.h>
170 #include <dt-bindings/power/mt8173-power.h>
173 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
174 reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
175 reg-names = "mac", "ippc";
176 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
177 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
178 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
179 clock-names = "sys_ck", "ref_ck";
180 phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
181 vusb33-supply = <&mt6397_vusb_reg>;
182 vbus-supply = <&usb_p1_vbus>;
183 imod-interval-ns = <10000>;
184 mediatek,syscon-wakeup = <&pericfg 0x400 1>;