1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 NXP
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: NXP iMX8MP Soc USB Controller
11 - Li Jun <jun.li@nxp.com>
15 const: fsl,imx8mp-dwc3
19 description: Address and length of the register set for the wrapper of
30 See section 2.3.9 of the DeviceTree Specification.
36 description: The interrupt that is asserted when a wakeup event is
41 A list of phandle and clock-specifier pairs for the clocks
42 listed in clock-names.
44 - description: system hsio root clock.
45 - description: suspend clock, used for usb wakeup logic.
52 # Required child node:
58 A child node must exist to represent the core DWC3 IP block
59 The content of the node is defined in dwc3.txt.
72 additionalProperties: false
76 #include <dt-bindings/clock/imx8mp-clock.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 usb3_0: usb@32f10100 {
79 compatible = "fsl,imx8mp-dwc3";
80 reg = <0x32f10100 0x8>;
81 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
82 <&clk IMX8MP_CLK_USB_ROOT>;
83 clock-names = "hsio", "suspend";
84 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
87 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
91 compatible = "snps,dwc3";
92 reg = <0x38100000 0x10000>;
93 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
94 <&clk IMX8MP_CLK_USB_CORE_REF>,
95 <&clk IMX8MP_CLK_USB_ROOT>;
96 clock-names = "bus_early", "ref", "suspend";
97 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
98 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
99 assigned-clock-rates = <500000000>;
100 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
101 phys = <&usb3_phy0>, <&usb3_phy0>;
102 phy-names = "usb2-phy", "usb3-phy";
103 snps,dis-u2-freeclk-exists-quirk;