Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (c) 2020 NXP
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: NXP iMX8MP Soc USB Controller
   9
  10 maintainers:
  11   - Li Jun <jun.li@nxp.com>
  12
  13 properties:
  14   compatible:
  15     const: fsl,imx8mp-dwc3
  16
  17   reg:
  18     items:
  19       - description: Address and length of the register set for HSIO Block Control
  20       - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
  21
  22   "#address-cells":
  23     enum: [ 1, 2 ]
  24
  25   "#size-cells":
  26     enum: [ 1, 2 ]
  27
  28   dma-ranges:
  29     description:
  30       See section 2.3.9 of the DeviceTree Specification.
  31
  32   ranges: true
  33
  34   interrupts:
  35     maxItems: 1
  36     description: The interrupt that is asserted when a wakeup event is
  37       received.
  38
  39   clocks:
  40     description:
  41       A list of phandle and clock-specifier pairs for the clocks
  42       listed in clock-names.
  43     items:
  44       - description: system hsio root clock.
  45       - description: suspend clock, used for usb wakeup logic.
  46
  47   clock-names:
  48     items:
  49       - const: hsio
  50       - const: suspend
  51
  52   fsl,permanently-attached:
  53     type: boolean
  54     description:
  55       Indicates if the device atached to a downstream port is
  56       permanently attached.
  57
  58   fsl,disable-port-power-control:
  59     type: boolean
  60     description:
  61       Indicates whether the host controller implementation includes port
  62       power control. Defines Bit 3 in capability register (HCCPARAMS).
  63
  64   fsl,over-current-active-low:
  65     type: boolean
  66     description:
  67       Over current signal polarity is active low.
  68
  69   fsl,power-active-low:
  70     type: boolean
  71     description:
  72       Power pad (PWR) polarity is active low.
  73
  74 # Required child node:
  75
  76 patternProperties:
  77   "^usb@[0-9a-f]+$":
  78     $ref: snps,dwc3.yaml#
  79
  80 required:
  81   - compatible
  82   - reg
  83   - "#address-cells"
  84   - "#size-cells"
  85   - dma-ranges
  86   - ranges
  87   - clocks
  88   - clock-names
  89   - interrupts
  90
  91 additionalProperties: false
  92
  93 examples:
  94   - |
  95     #include <dt-bindings/clock/imx8mp-clock.h>
  96     #include <dt-bindings/interrupt-controller/arm-gic.h>
  97     usb3_0: usb@32f10100 {
  98       compatible = "fsl,imx8mp-dwc3";
  99       reg = <0x32f10100 0x8>,
 100             <0x381f0000 0x20>;
 101       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 102                <&clk IMX8MP_CLK_USB_ROOT>;
 103       clock-names = "hsio", "suspend";
 104       interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 105       #address-cells = <1>;
 106       #size-cells = <1>;
 107       dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 108       ranges;
 109
 110       usb@38100000 {
 111         compatible = "snps,dwc3";
 112         reg = <0x38100000 0x10000>;
 113         clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 114                  <&clk IMX8MP_CLK_USB_CORE_REF>,
 115                  <&clk IMX8MP_CLK_USB_ROOT>;
 116         clock-names = "bus_early", "ref", "suspend";
 117         assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 118         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 119         assigned-clock-rates = <500000000>;
 120         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 121         phys = <&usb3_phy0>, <&usb3_phy0>;
 122         phy-names = "usb2-phy", "usb3-phy";
 123         snps,dis-u2-freeclk-exists-quirk;
 124       };
 125     };