1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
31 description: specifies a phandle to PM domain provider node
36 A list of phandle and clock-specifier pairs for the clocks
37 listed in clock-names.
39 - description: Master/Core clock, has to be >= 125 MHz
40 for SS operation and >= 60MHz for HS operation.
41 - description: Clock source to core during PHY power down.
50 A list of phandles for resets listed in reset-names.
53 - description: USB core reset
54 - description: USB hibernation reset
55 - description: USB APB reset
76 description: GPIO used for the reset ulpi-phy
79 # Required child node:
97 additionalProperties: false
101 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
102 #include <dt-bindings/power/xlnx-zynqmp-power.h>
103 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
104 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
105 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
106 #include <dt-bindings/phy/phy.h>
108 #address-cells = <2>;
112 #address-cells = <0x2>;
114 compatible = "xlnx,zynqmp-dwc3";
115 reg = <0x0 0xff9d0000 0x0 0x100>;
116 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
117 clock-names = "bus_clk", "ref_clk";
118 power-domains = <&zynqmp_firmware PD_USB_0>;
119 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
120 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
121 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
122 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
123 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
124 phy-names = "usb3-phy";
128 compatible = "snps,dwc3";
129 reg = <0x0 0xfe200000 0x0 0x40000>;
130 interrupt-names = "host", "otg";
131 interrupts = <0 65 4>, <0 69 4>;