1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 BayLibre, SAS
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
23 connected to the Glue to serve as OTG ID change detection.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
31 - amlogic,meson-g12a-usb-ctrl
32 - amlogic,meson-a1-usb-ctrl
56 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
57 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
58 - const: usb3-phy0 # USB3 PHY if USB3_0 is used
70 description: VBUS power supply when used in OTG switchable mode
76 additionalProperties: false
96 - amlogic,meson-a1-usb-ctrl
106 - const: xtal_usb_ctrl
113 compatible = "amlogic,meson-g12a-usb-ctrl";
114 reg = <0xffe09000 0xa0>;
116 #address-cells = <1>;
120 clocks = <&clkc_usb>;
121 resets = <&reset_usb>;
125 phys = <&usb2_phy0>, <&usb2_phy1>, <&usb3_phy0>;
126 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
129 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
130 reg = <0xff400000 0x40000>;
132 clocks = <&clkc_usb1>;
135 dr_mode = "peripheral";
136 g-rx-fifo-size = <192>;
137 g-np-tx-fifo-size = <128>;
138 g-tx-fifo-size = <128 128 16 16 16>;
142 compatible = "snps,dwc3";
143 reg = <0xff500000 0x100000>;
146 snps,dis_u2_susphy_quirk;
147 snps,quirk-frame-length-adjustment;