Documentation/devicetree/bindings/timer/renesas,cmt.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/timer/renesas,cmt.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas Compare Match Timer (CMT)
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11   - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  12
  13 description:
  14   The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
  15   inputs and programmable compare match.
  16
  17   Channels share hardware resources but their counter and compare match values
  18   are independent. A particular CMT instance can implement only a subset of the
  19   channels supported by the CMT model. Channel indices represent the hardware
  20   position of the channel in the CMT and don't match the channel numbers in the
  21   datasheets.
  22
  23 properties:
  24   compatible:
  25     oneOf:
  26       - items:
  27           - enum:
  28               - renesas,r8a7740-cmt0      # 32-bit CMT0 on R-Mobile A1
  29               - renesas,r8a7740-cmt1      # 48-bit CMT1 on R-Mobile A1
  30               - renesas,r8a7740-cmt2      # 32-bit CMT2 on R-Mobile A1
  31               - renesas,r8a7740-cmt3      # 32-bit CMT3 on R-Mobile A1
  32               - renesas,r8a7740-cmt4      # 32-bit CMT4 on R-Mobile A1
  33               - renesas,sh73a0-cmt0       # 32-bit CMT0 on SH-Mobile AG5
  34               - renesas,sh73a0-cmt1       # 48-bit CMT1 on SH-Mobile AG5
  35               - renesas,sh73a0-cmt2       # 32-bit CMT2 on SH-Mobile AG5
  36               - renesas,sh73a0-cmt3       # 32-bit CMT3 on SH-Mobile AG5
  37               - renesas,sh73a0-cmt4       # 32-bit CMT4 on SH-Mobile AG5
  38
  39       - items:
  40           - enum:
  41               - renesas,r8a73a4-cmt0      # 32-bit CMT0 on R-Mobile APE6
  42               - renesas,r8a7742-cmt0      # 32-bit CMT0 on RZ/G1H
  43               - renesas,r8a7743-cmt0      # 32-bit CMT0 on RZ/G1M
  44               - renesas,r8a7744-cmt0      # 32-bit CMT0 on RZ/G1N
  45               - renesas,r8a7745-cmt0      # 32-bit CMT0 on RZ/G1E
  46               - renesas,r8a77470-cmt0     # 32-bit CMT0 on RZ/G1C
  47               - renesas,r8a7790-cmt0      # 32-bit CMT0 on R-Car H2
  48               - renesas,r8a7791-cmt0      # 32-bit CMT0 on R-Car M2-W
  49               - renesas,r8a7792-cmt0      # 32-bit CMT0 on R-Car V2H
  50               - renesas,r8a7793-cmt0      # 32-bit CMT0 on R-Car M2-N
  51               - renesas,r8a7794-cmt0      # 32-bit CMT0 on R-Car E2
  52           - const: renesas,rcar-gen2-cmt0 # 32-bit CMT0 on R-Mobile APE6, R-Car Gen2 and RZ/G1
  53
  54       - items:
  55           - enum:
  56               - renesas,r8a73a4-cmt1      # 48-bit CMT1 on R-Mobile APE6
  57               - renesas,r8a7742-cmt1      # 48-bit CMT1 on RZ/G1H
  58               - renesas,r8a7743-cmt1      # 48-bit CMT1 on RZ/G1M
  59               - renesas,r8a7744-cmt1      # 48-bit CMT1 on RZ/G1N
  60               - renesas,r8a7745-cmt1      # 48-bit CMT1 on RZ/G1E
  61               - renesas,r8a77470-cmt1     # 48-bit CMT1 on RZ/G1C
  62               - renesas,r8a7790-cmt1      # 48-bit CMT1 on R-Car H2
  63               - renesas,r8a7791-cmt1      # 48-bit CMT1 on R-Car M2-W
  64               - renesas,r8a7792-cmt1      # 48-bit CMT1 on R-Car V2H
  65               - renesas,r8a7793-cmt1      # 48-bit CMT1 on R-Car M2-N
  66               - renesas,r8a7794-cmt1      # 48-bit CMT1 on R-Car E2
  67           - const: renesas,rcar-gen2-cmt1 # 48-bit CMT1 on R-Mobile APE6, R-Car Gen2 and RZ/G1
  68
  69       - items:
  70           - enum:
  71               - renesas,r8a774a1-cmt0     # 32-bit CMT0 on RZ/G2M
  72               - renesas,r8a774b1-cmt0     # 32-bit CMT0 on RZ/G2N
  73               - renesas,r8a774c0-cmt0     # 32-bit CMT0 on RZ/G2E
  74               - renesas,r8a774e1-cmt0     # 32-bit CMT0 on RZ/G2H
  75               - renesas,r8a7795-cmt0      # 32-bit CMT0 on R-Car H3
  76               - renesas,r8a7796-cmt0      # 32-bit CMT0 on R-Car M3-W
  77               - renesas,r8a77961-cmt0     # 32-bit CMT0 on R-Car M3-W+
  78               - renesas,r8a77965-cmt0     # 32-bit CMT0 on R-Car M3-N
  79               - renesas,r8a77970-cmt0     # 32-bit CMT0 on R-Car V3M
  80               - renesas,r8a77980-cmt0     # 32-bit CMT0 on R-Car V3H
  81               - renesas,r8a77990-cmt0     # 32-bit CMT0 on R-Car E3
  82               - renesas,r8a77995-cmt0     # 32-bit CMT0 on R-Car D3
  83               - renesas,r8a779a0-cmt0     # 32-bit CMT0 on R-Car V3U
  84           - const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2
  85
  86       - items:
  87           - enum:
  88               - renesas,r8a774a1-cmt1     # 48-bit CMT on RZ/G2M
  89               - renesas,r8a774b1-cmt1     # 48-bit CMT on RZ/G2N
  90               - renesas,r8a774c0-cmt1     # 48-bit CMT on RZ/G2E
  91               - renesas,r8a774e1-cmt1     # 48-bit CMT on RZ/G2H
  92               - renesas,r8a7795-cmt1      # 48-bit CMT on R-Car H3
  93               - renesas,r8a7796-cmt1      # 48-bit CMT on R-Car M3-W
  94               - renesas,r8a77961-cmt1     # 48-bit CMT on R-Car M3-W+
  95               - renesas,r8a77965-cmt1     # 48-bit CMT on R-Car M3-N
  96               - renesas,r8a77970-cmt1     # 48-bit CMT on R-Car V3M
  97               - renesas,r8a77980-cmt1     # 48-bit CMT on R-Car V3H
  98               - renesas,r8a77990-cmt1     # 48-bit CMT on R-Car E3
  99               - renesas,r8a77995-cmt1     # 48-bit CMT on R-Car D3
 100               - renesas,r8a779a0-cmt1     # 48-bit CMT on R-Car V3U
 101           - const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2
 102
 103   reg:
 104     maxItems: 1
 105
 106   interrupts:
 107     minItems: 1
 108     maxItems: 8
 109
 110   clocks:
 111     maxItems: 1
 112
 113   clock-names:
 114     const: fck
 115
 116   power-domains:
 117     maxItems: 1
 118
 119   resets:
 120     maxItems: 1
 121
 122 required:
 123   - compatible
 124   - reg
 125   - interrupts
 126   - clocks
 127   - clock-names
 128   - power-domains
 129
 130 allOf:
 131   - if:
 132       properties:
 133         compatible:
 134           contains:
 135             enum:
 136               - renesas,rcar-gen2-cmt0
 137               - renesas,rcar-gen3-cmt0
 138     then:
 139       properties:
 140         interrupts:
 141           minItems: 2
 142           maxItems: 2
 143
 144   - if:
 145       properties:
 146         compatible:
 147           contains:
 148             enum:
 149               - renesas,rcar-gen2-cmt1
 150               - renesas,rcar-gen3-cmt1
 151     then:
 152       properties:
 153         interrupts:
 154           minItems: 8
 155           maxItems: 8
 156
 157 additionalProperties: false
 158
 159 examples:
 160   - |
 161     #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
 162     #include <dt-bindings/interrupt-controller/arm-gic.h>
 163     #include <dt-bindings/power/r8a7790-sysc.h>
 164     cmt0: timer@ffca0000 {
 165             compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
 166             reg = <0xffca0000 0x1004>;
 167             interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 168                          <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 169             clocks = <&cpg CPG_MOD 124>;
 170             clock-names = "fck";
 171             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 172             resets = <&cpg 124>;
 173     };
 174
 175     cmt1: timer@e6130000 {
 176             compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
 177             reg = <0xe6130000 0x1004>;
 178             interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 179                          <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 180                          <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 181                          <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 182                          <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 183                          <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 184                          <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 185                          <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 186             clocks = <&cpg CPG_MOD 329>;
 187             clock-names = "fck";
 188             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 189             resets = <&cpg 329>;
 190     };