1 * Renesas R-Car Compare Match Timer (CMT)
3 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
4 inputs and programmable compare match.
6 Channels share hardware resources but their counter and compare match value
7 are independent. A particular CMT instance can implement only a subset of the
8 channels supported by the CMT model. Channel indices represent the hardware
9 position of the channel in the CMT and don't match the channel numbers in the
14 - compatible: must contain one or more of the following:
15 - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
17 - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
19 - "renesas,cmt-48" for all non-second generation 48-bit CMT
20 (CMT1 on sh73a0 and r8a7740)
21 This is a fallback for the above renesas,cmt-48-* entries.
23 - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
24 - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
25 - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
26 - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743.
27 - "renesas,r8a7744-cmt0" for the 32-bit CMT0 device included in r8a7744.
28 - "renesas,r8a7744-cmt1" for the 48-bit CMT1 device included in r8a7744.
29 - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.
30 - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745.
31 - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470.
32 - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470.
33 - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1.
34 - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1.
35 - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
36 - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
37 - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
38 - "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791.
39 - "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793.
40 - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793.
41 - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.
42 - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.
43 - "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796.
44 - "renesas,r8a7796-cmt1" for the 48-bit CMT1 device included in r8a7796.
45 - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970.
46 - "renesas,r8a77970-cmt1" for the 48-bit CMT1 device included in r8a77970.
47 - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980.
48 - "renesas,r8a77980-cmt1" for the 48-bit CMT1 device included in r8a77980.
50 - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2
52 - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2
54 These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries
56 - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3
58 - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3
60 These are fallbacks for R-Car Gen3 and RZ/G2 entries listed
63 - reg: base address and length of the registers block for the timer module.
64 - interrupts: interrupt-specifier for the timer, one per channel.
65 - clocks: a list of phandle + clock-specifier pairs, one for each entry
67 - clock-names: must contain "fck" for the functional clock.
70 Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
72 cmt0: timer@ffca0000 {
73 compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
74 reg = <0 0xffca0000 0 0x1004>;
75 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
76 <0 142 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
81 cmt1: timer@e6130000 {
82 compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
83 reg = <0 0xe6130000 0 0x1004>;
84 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
85 <0 121 IRQ_TYPE_LEVEL_HIGH>,
86 <0 122 IRQ_TYPE_LEVEL_HIGH>,
87 <0 123 IRQ_TYPE_LEVEL_HIGH>,
88 <0 124 IRQ_TYPE_LEVEL_HIGH>,
89 <0 125 IRQ_TYPE_LEVEL_HIGH>,
90 <0 126 IRQ_TYPE_LEVEL_HIGH>,
91 <0 127 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;