1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 # Copyright 2019 Linaro Ltd.
5 $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: QCOM SoC Temperature Sensor (TSENS)
11 - Amit Kucheria <amitk@kernel.org>
14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15 three distinct major versions of the IP that is supported by a single driver.
16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17 everything before v1 when there was no versioning information.
22 - description: msm9860 TSENS based
27 - description: v0.1 of TSENS
34 - const: qcom,tsens-v0_1
36 - description: v1 of TSENS
41 - const: qcom,tsens-v1
43 - description: v2 of TSENS
53 - const: qcom,tsens-v2
57 - description: TM registers
58 - description: SROT registers
63 - description: Combined interrupt if upper or lower threshold crossed
64 - description: Interrupt if critical threshold crossed
76 Reference to an nvmem node for the calibration data
89 Number of sensors enabled on this platform
90 $ref: /schemas/types.yaml#/definitions/uint32
94 "#thermal-sensor-cells":
97 Number of cells required to uniquely identify the thermal sensors. Since
98 we have multiple sensors this is set to 1
104 - "#thermal-sensor-cells"
148 additionalProperties: false
152 #include <dt-bindings/interrupt-controller/arm-gic.h>
153 // Example msm9860 based SoC (ipq8064):
154 gcc: clock-controller {
158 tsens: thermal-sensor {
159 compatible = "qcom,ipq8064-tsens";
161 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
162 nvmem-cell-names = "calib", "calib_backup";
163 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "uplow";
166 #qcom,sensors = <11>;
167 #thermal-sensor-cells = <1>;
172 #include <dt-bindings/interrupt-controller/arm-gic.h>
173 // Example 1 (legacy: for pre v1 IP):
174 tsens1: thermal-sensor@900000 {
175 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
176 reg = <0x4a9000 0x1000>, /* TM */
177 <0x4a8000 0x1000>; /* SROT */
179 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
180 nvmem-cell-names = "calib", "calib_sel";
182 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
183 interrupt-names = "uplow";
186 #thermal-sensor-cells = <1>;
190 #include <dt-bindings/interrupt-controller/arm-gic.h>
191 // Example 2 (for any platform containing v1 of the TSENS IP):
192 tsens2: thermal-sensor@4a9000 {
193 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
194 reg = <0x004a9000 0x1000>, /* TM */
195 <0x004a8000 0x1000>; /* SROT */
197 nvmem-cells = <&tsens_caldata>;
198 nvmem-cell-names = "calib";
200 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-names = "uplow";
203 #qcom,sensors = <10>;
204 #thermal-sensor-cells = <1>;
208 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 // Example 3 (for any platform containing v2 of the TSENS IP):
210 tsens3: thermal-sensor@c263000 {
211 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
212 reg = <0xc263000 0x1ff>,
215 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-names = "uplow", "critical";
219 #qcom,sensors = <13>;
220 #thermal-sensor-cells = <1>;