1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
13 Simple IO memory regions to be managed by the genalloc API.
15 Each child of the sram node specifies a region of reserved memory. Each
16 child node should use a 'reg' property to specify a specific range of
19 Following the generic-names recommended practice, node names should
20 reflect the purpose of the node. Unit address (@<address>) should be
25 pattern: "^sram(@.*)?"
31 - atmel,sama5d2-securam
32 - rockchip,rk3288-pmu-sram
40 A list of phandle and clock specifier pair that controls the single
52 Should translate from local addresses within the sram to bus addresses.
56 The flag indicating, that SRAM memory region has not to be remapped
57 as write combining. WC is used by default.
61 "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
64 Each child of the sram node specifies a region of reserved memory.
68 Should contain a vendor specific string in the form
69 <vendor>,[<device>-]<usage>
72 - allwinner,sun4i-a10-sram-a3-a4
73 - allwinner,sun4i-a10-sram-c1
74 - allwinner,sun4i-a10-sram-d
75 - allwinner,sun9i-a80-smp-sram
76 - allwinner,sun50i-a64-sram-c
77 - amlogic,meson8-ao-arc-sram
78 - amlogic,meson8b-ao-arc-sram
79 - amlogic,meson8-smp-sram
80 - amlogic,meson8b-smp-sram
81 - amlogic,meson-gxbb-scp-shmem
82 - amlogic,meson-axg-scp-shmem
85 - rockchip,rk3066-smp-sram
86 - samsung,exynos4210-sysram
87 - samsung,exynos4210-sysram-ns
88 - socionext,milbeaut-smp-sram
92 IO mem address range, relative to the SRAM range.
97 Indicates that the particular reserved SRAM area is addressable
98 and in use by another device or devices.
103 Indicates that the reserved SRAM area may be accessed outside
104 of the kernel, e.g. by bootloader or userspace.
109 Same as 'pool' above but with the additional constraint that code
110 will be run from the region and that the memory is maintained as
111 read-only, executable during code execution. NOTE: This region must
112 be page aligned on start and end in order to properly allow
113 manipulation of the page attributes.
118 The name for the reserved partition, if omitted, the label is taken
119 from the node name excluding the unit address.
124 additionalProperties: false
134 const: rockchip,rk3288-pmu-sram
142 additionalProperties: false
147 compatible = "mmio-sram";
148 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
150 #address-cells = <1>;
152 ranges = <0 0x5c000000 0x40000>;
159 reg = <0x1000 0x1000>;
163 exported-sram@20000 {
164 reg = <0x20000 0x20000>;
170 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
171 // of the secondary cores. Once the core gets powered up it executes the
172 // code that is residing at some specific location of the SYSRAM.
174 // Therefore reserved section sub-nodes have to be added to the mmio-sram
175 // declaration. These nodes are of two types depending upon secure or
176 // non-secure execution environment.
178 compatible = "mmio-sram";
179 reg = <0x02020000 0x54000>;
180 #address-cells = <1>;
182 ranges = <0 0x02020000 0x54000>;
185 compatible = "samsung,exynos4210-sysram";
190 compatible = "samsung,exynos4210-sysram-ns";
191 reg = <0x53000 0x1000>;
196 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
197 // Once the core gets powered up it executes the code that is residing at a
198 // specific location.
200 // Therefore a reserved section sub-node has to be added to the mmio-sram
203 compatible = "mmio-sram";
204 reg = <0xd9000000 0x20000>;
205 #address-cells = <1>;
207 ranges = <0 0xd9000000 0x20000>;
210 compatible = "amlogic,meson8b-smp-sram";
217 compatible = "mmio-sram";
218 reg = <0xe63c0000 0x1000>;
219 #address-cells = <1>;
221 ranges = <0 0xe63c0000 0x1000>;
224 compatible = "renesas,smp-sram";
231 compatible = "mmio-sram";
232 reg = <0x10080000 0x10000>;
233 #address-cells = <1>;
238 compatible = "rockchip,rk3066-smp-sram";
239 reg = <0x10080000 0x50>;
244 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
245 // resume from maskrom(the 1st level loader). This is a common use of
246 // the "pmu-sram" because it keeps power even in low power states
249 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
250 reg = <0xff720000 0x1000>;
254 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
255 // primary core (cpu0). Once the core gets powered up it checks if a magic
256 // value is set at a specific location. If it is then the BROM will jump
257 // to the software entry address, instead of executing a standard boot.
259 // Also there are no "secure-only" properties. The implementation should
260 // check if this SRAM is usable first.
262 // 256 KiB secure SRAM at 0x20000
263 compatible = "mmio-sram";
264 reg = <0x00020000 0x40000>;
265 #address-cells = <1>;
267 ranges = <0 0x00020000 0x40000>;
270 // This is checked by BROM to determine if
271 // cpu0 should jump to SMP entry vector
272 compatible = "allwinner,sun9i-a80-smp-sram";
279 compatible = "mmio-sram";
281 #address-cells = <1>;
283 ranges = <0 0x0 0x10000>;
286 compatible = "socionext,milbeaut-smp-sram";