1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
13 Simple IO memory regions to be managed by the genalloc API.
15 Each child of the sram node specifies a region of reserved memory. Each
16 child node should use a 'reg' property to specify a specific range of
19 Following the generic-names recommended practice, node names should
20 reflect the purpose of the node. Unit address (@<address>) should be
25 pattern: "^sram(@.*)?"
31 - amlogic,meson-gxbb-sram
33 - atmel,sama5d2-securam
34 - rockchip,rk3288-pmu-sram
42 A list of phandle and clock specifier pair that controls the single
54 Should translate from local addresses within the sram to bus addresses.
58 The flag indicating, that SRAM memory region has not to be remapped
59 as write combining. WC is used by default.
63 "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
66 Each child of the sram node specifies a region of reserved memory.
70 Should contain a vendor specific string in the form
71 <vendor>,[<device>-]<usage>
74 - allwinner,sun4i-a10-sram-a3-a4
75 - allwinner,sun4i-a10-sram-c1
76 - allwinner,sun4i-a10-sram-d
77 - allwinner,sun9i-a80-smp-sram
78 - allwinner,sun50i-a64-sram-c
79 - amlogic,meson8-ao-arc-sram
80 - amlogic,meson8b-ao-arc-sram
81 - amlogic,meson8-smp-sram
82 - amlogic,meson8b-smp-sram
83 - amlogic,meson-gxbb-scp-shmem
84 - amlogic,meson-axg-scp-shmem
89 - rockchip,rk3066-smp-sram
90 - samsung,exynos4210-sysram
91 - samsung,exynos4210-sysram-ns
92 - socionext,milbeaut-smp-sram
96 IO mem address range, relative to the SRAM range.
101 Indicates that the particular reserved SRAM area is addressable
102 and in use by another device or devices.
107 Indicates that the reserved SRAM area may be accessed outside
108 of the kernel, e.g. by bootloader or userspace.
113 Same as 'pool' above but with the additional constraint that code
114 will be run from the region and that the memory is maintained as
115 read-only, executable during code execution. NOTE: This region must
116 be page aligned on start and end in order to properly allow
117 manipulation of the page attributes.
122 The name for the reserved partition, if omitted, the label is taken
123 from the node name excluding the unit address.
128 additionalProperties: false
138 const: rockchip,rk3288-pmu-sram
146 additionalProperties: false
151 compatible = "mmio-sram";
152 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
154 #address-cells = <1>;
156 ranges = <0 0x5c000000 0x40000>;
163 reg = <0x1000 0x1000>;
167 exported-sram@20000 {
168 reg = <0x20000 0x20000>;
174 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
175 // of the secondary cores. Once the core gets powered up it executes the
176 // code that is residing at some specific location of the SYSRAM.
178 // Therefore reserved section sub-nodes have to be added to the mmio-sram
179 // declaration. These nodes are of two types depending upon secure or
180 // non-secure execution environment.
182 compatible = "mmio-sram";
183 reg = <0x02020000 0x54000>;
184 #address-cells = <1>;
186 ranges = <0 0x02020000 0x54000>;
189 compatible = "samsung,exynos4210-sysram";
194 compatible = "samsung,exynos4210-sysram-ns";
195 reg = <0x53000 0x1000>;
200 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
201 // Once the core gets powered up it executes the code that is residing at a
202 // specific location.
204 // Therefore a reserved section sub-node has to be added to the mmio-sram
207 compatible = "mmio-sram";
208 reg = <0xd9000000 0x20000>;
209 #address-cells = <1>;
211 ranges = <0 0xd9000000 0x20000>;
214 compatible = "amlogic,meson8b-smp-sram";
221 compatible = "mmio-sram";
222 reg = <0xe63c0000 0x1000>;
223 #address-cells = <1>;
225 ranges = <0 0xe63c0000 0x1000>;
228 compatible = "renesas,smp-sram";
235 compatible = "mmio-sram";
236 reg = <0x10080000 0x10000>;
237 #address-cells = <1>;
242 compatible = "rockchip,rk3066-smp-sram";
243 reg = <0x10080000 0x50>;
248 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
249 // resume from maskrom(the 1st level loader). This is a common use of
250 // the "pmu-sram" because it keeps power even in low power states
253 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
254 reg = <0xff720000 0x1000>;
258 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
259 // primary core (cpu0). Once the core gets powered up it checks if a magic
260 // value is set at a specific location. If it is then the BROM will jump
261 // to the software entry address, instead of executing a standard boot.
263 // Also there are no "secure-only" properties. The implementation should
264 // check if this SRAM is usable first.
266 // 256 KiB secure SRAM at 0x20000
267 compatible = "mmio-sram";
268 reg = <0x00020000 0x40000>;
269 #address-cells = <1>;
271 ranges = <0 0x00020000 0x40000>;
274 // This is checked by BROM to determine if
275 // cpu0 should jump to SMP entry vector
276 compatible = "allwinner,sun9i-a80-smp-sram";
283 compatible = "mmio-sram";
285 #address-cells = <1>;
287 ranges = <0 0x0 0x10000>;
290 compatible = "socionext,milbeaut-smp-sram";