1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
24 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
25 Supported compatible strings are -
26 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27 onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
28 SPI v0 IP block with no chip integration tweaks.
29 Please refer to sifive-blocks-ip-versioning.txt for details
31 SPI RTL that corresponds to the IP block version numbers can be found here -
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
37 - description: SPI registers region
38 - description: Memory mapped flash region
47 Must reference the frequency given to the controller
51 Depth of hardware queues; defaults to 8
52 $ref: "/schemas/types.yaml#/definitions/uint32"
56 sifive,max-bits-per-word:
58 Maximum bits per word; defaults to 8
59 $ref: "/schemas/types.yaml#/definitions/uint32"
60 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
69 unevaluatedProperties: false
74 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
75 reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
76 interrupt-parent = <&plic>;
81 sifive,fifo-depth = <8>;
82 sifive,max-bits-per-word = <8>;