Merge branch 'address-masking'
[linux-2.6-microblaze.git] / Documentation / devicetree / bindings / spi / spi-fsl-lpspi.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Freescale Low Power SPI (LPSPI) for i.MX
8
9 maintainers:
10   - Shawn Guo <shawnguo@kernel.org>
11   - Sascha Hauer <s.hauer@pengutronix.de>
12   - Fabio Estevam <festevam@gmail.com>
13
14 allOf:
15   - $ref: /schemas/spi/spi-controller.yaml#
16
17 properties:
18   compatible:
19     oneOf:
20       - enum:
21           - fsl,imx7ulp-spi
22           - fsl,imx8qxp-spi
23       - items:
24           - enum:
25               - fsl,imx8ulp-spi
26               - fsl,imx93-spi
27               - fsl,imx95-spi
28           - const: fsl,imx7ulp-spi
29   reg:
30     maxItems: 1
31
32   interrupts:
33     maxItems: 1
34
35   clocks:
36     items:
37       - description: SoC SPI per clock
38       - description: SoC SPI ipg clock
39
40   clock-names:
41     items:
42       - const: per
43       - const: ipg
44
45   dmas:
46     items:
47       - description: TX DMA Channel
48       - description: RX DMA Channel
49
50   dma-names:
51     items:
52       - const: tx
53       - const: rx
54
55   fsl,spi-only-use-cs1-sel:
56     description:
57       spi common code does not support use of CS signals discontinuously.
58       i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
59       this property to re-config the chipselect value in the LPSPI driver.
60     type: boolean
61
62   num-cs:
63     description:
64       number of chip selects.
65     minimum: 1
66     maximum: 2
67     default: 1
68
69   power-domains:
70     maxItems: 1
71
72 required:
73   - compatible
74   - reg
75   - interrupts
76   - clocks
77   - clock-names
78
79 unevaluatedProperties: false
80
81 examples:
82   - |
83     #include <dt-bindings/clock/imx7ulp-clock.h>
84     #include <dt-bindings/interrupt-controller/arm-gic.h>
85
86     spi@40290000 {
87         compatible = "fsl,imx7ulp-spi";
88         reg = <0x40290000 0x10000>;
89         interrupt-parent = <&intc>;
90         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
91         clocks = <&clks IMX7ULP_CLK_LPSPI2>,
92                  <&clks IMX7ULP_CLK_DUMMY>;
93         clock-names = "per", "ipg";
94         spi-slave;
95         fsl,spi-only-use-cs1-sel;
96         num-cs = <2>;
97     };