Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale Low Power SPI (LPSPI) for i.MX
   8
   9 maintainers:
  10   - Anson Huang <Anson.Huang@nxp.com>
  11
  12 allOf:
  13   - $ref: /schemas/spi/spi-controller.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - enum:
  19           - fsl,imx7ulp-spi
  20           - fsl,imx8qxp-spi
  21       - items:
  22           - enum:
  23               - fsl,imx8ulp-spi
  24               - fsl,imx93-spi
  25           - const: fsl,imx7ulp-spi
  26   reg:
  27     maxItems: 1
  28
  29   interrupts:
  30     maxItems: 1
  31
  32   clocks:
  33     items:
  34       - description: SoC SPI per clock
  35       - description: SoC SPI ipg clock
  36
  37   clock-names:
  38     items:
  39       - const: per
  40       - const: ipg
  41
  42   dmas:
  43     items:
  44       - description: TX DMA Channel
  45       - description: RX DMA Channel
  46
  47   dma-names:
  48     items:
  49       - const: tx
  50       - const: rx
  51
  52   fsl,spi-only-use-cs1-sel:
  53     description:
  54       spi common code does not support use of CS signals discontinuously.
  55       i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
  56       this property to re-config the chipselect value in the LPSPI driver.
  57     type: boolean
  58
  59   num-cs:
  60     description:
  61       number of chip selects.
  62     minimum: 1
  63     maximum: 2
  64     default: 1
  65
  66 required:
  67   - compatible
  68   - reg
  69   - interrupts
  70   - clocks
  71   - clock-names
  72
  73 unevaluatedProperties: false
  74
  75 examples:
  76   - |
  77     #include <dt-bindings/clock/imx7ulp-clock.h>
  78     #include <dt-bindings/interrupt-controller/arm-gic.h>
  79
  80     spi@40290000 {
  81         compatible = "fsl,imx7ulp-spi";
  82         reg = <0x40290000 0x10000>;
  83         interrupt-parent = <&intc>;
  84         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  85         clocks = <&clks IMX7ULP_CLK_LPSPI2>,
  86                  <&clks IMX7ULP_CLK_DUMMY>;
  87         clock-names = "per", "ipg";
  88         spi-slave;
  89         fsl,spi-only-use-cs1-sel;
  90         num-cs = <2>;
  91     };