1 Renesas MSIOF spi controller
4 - compatible : "renesas,msiof-<soctype>" for SoCs,
5 "renesas,sh-msiof" for SuperH, or
6 "renesas,sh-mobile-msiof" for SH Mobile series.
7 Examples with soctypes are:
8 "renesas,msiof-r8a7790" (R-Car H2)
9 "renesas,msiof-r8a7791" (R-Car M2-W)
10 "renesas,msiof-r8a7792" (R-Car V2H)
11 "renesas,msiof-r8a7793" (R-Car M2-N)
12 "renesas,msiof-r8a7794" (R-Car E2)
13 "renesas,msiof-r8a7796" (R-Car M3-W)
14 "renesas,msiof-sh73a0" (SH-Mobile AG5)
15 - reg : A list of offsets and lengths of the register sets for
17 If only one register set is present, it is to be used
18 by both the CPU and the DMA engine.
19 If two register sets are present, the first is to be
20 used by the CPU, and the second is to be used by the
22 - interrupt-parent : The phandle for the interrupt controller that
23 services interrupts for this device
24 - interrupts : Interrupt specifier
25 - #address-cells : Must be <1>
26 - #size-cells : Must be <0>
29 - clocks : Must contain a reference to the functional clock.
30 - num-cs : Total number of chip-selects (default is 1)
31 - dmas : Must contain a list of two references to DMA
32 specifiers, one for transmission, and one for
34 - dma-names : Must contain a list of two DMA names, "tx" and "rx".
35 - renesas,dtdl : delay sync signal (setup) in transmit mode.
36 Must contain one of the following values:
38 50 (0.5-clock-cycle delay)
39 100 (1-clock-cycle delay)
40 150 (1.5-clock-cycle delay)
41 200 (2-clock-cycle delay)
43 - renesas,syncdl : delay sync signal (hold) in transmit mode.
44 Must contain one of the following values:
46 50 (0.5-clock-cycle delay)
47 100 (1-clock-cycle delay)
48 150 (1.5-clock-cycle delay)
49 200 (2-clock-cycle delay)
50 300 (3-clock-cycle delay)
52 Optional properties, deprecated for soctype-specific bindings:
53 - renesas,tx-fifo-size : Overrides the default tx fifo size given in words
55 - renesas,rx-fifo-size : Overrides the default rx fifo size given in words
58 Pinctrl properties might be needed, too. See
59 Documentation/devicetree/bindings/pinctrl/renesas,*.
63 msiof0: spi@e6e20000 {
64 compatible = "renesas,msiof-r8a7791";
65 reg = <0 0xe6e20000 0 0x0064>;
66 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
67 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
68 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
69 dma-names = "tx", "rx";