1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 - $ref: "spi-controller.yaml#"
19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
59 nvidia,tx-clk-tap-delay:
61 Delays the clock going out to device with this tap value.
62 Tap value varies based on platform design trace lengths from Tegra
63 QSPI to corresponding slave device.
64 $ref: /schemas/types.yaml#/definitions/uint32
68 nvidia,rx-clk-tap-delay:
70 Delays the clock coming in from the device with this tap value.
71 Tap value varies based on platform design trace lengths from Tegra
72 QSPI to corresponding slave device.
73 $ref: /schemas/types.yaml#/definitions/uint32
88 unevaluatedProperties: false
92 #include <dt-bindings/clock/tegra210-car.h>
93 #include <dt-bindings/reset/tegra210-car.h>
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 compatible = "nvidia,tegra210-qspi";
97 reg = <0x70410000 0x1000>;
98 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&tegra_car TEGRA210_CLK_QSPI>,
102 <&tegra_car TEGRA210_CLK_QSPI_PM>;
103 clock-names = "qspi", "qspi_out";
104 resets = <&tegra_car 211>;
105 dmas = <&apbdma 5>, <&apbdma 5>;
106 dma-names = "rx", "tx";
109 compatible = "spi-nor";
111 spi-max-frequency = <104000000>;
112 spi-tx-bus-width = <2>;
113 spi-rx-bus-width = <2>;
114 nvidia,tx-clk-tap-delay = <0>;
115 nvidia,rx-clk-tap-delay = <0>;