Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Cadence Quad SPI controller
   8
   9 maintainers:
  10   - Pratyush Yadav <p.yadav@ti.com>
  11
  12 allOf:
  13   - $ref: spi-controller.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - ti,k2g-qspi
  21               - ti,am654-ospi
  22               - intel,lgm-qspi
  23           - const: cdns,qspi-nor
  24       - const: cdns,qspi-nor
  25
  26   reg:
  27     items:
  28       - description: the controller register set
  29       - description: the controller data area
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   clocks:
  35     maxItems: 1
  36
  37   cdns,fifo-depth:
  38     description:
  39       Size of the data FIFO in words.
  40     $ref: "/schemas/types.yaml#/definitions/uint32"
  41     enum: [ 128, 256 ]
  42     default: 128
  43
  44   cdns,fifo-width:
  45     $ref: /schemas/types.yaml#/definitions/uint32
  46     description:
  47       Bus width of the data FIFO in bytes.
  48     default: 4
  49
  50   cdns,trigger-address:
  51     $ref: /schemas/types.yaml#/definitions/uint32
  52     description:
  53       32-bit indirect AHB trigger address.
  54
  55   cdns,is-decoded-cs:
  56     type: boolean
  57     description:
  58       Flag to indicate whether decoder is used to select different chip select
  59       for different memory regions.
  60
  61   cdns,rclk-en:
  62     type: boolean
  63     description:
  64       Flag to indicate that QSPI return clock is used to latch the read
  65       data rather than the QSPI clock. Make sure that QSPI return clock
  66       is populated on the board before using this property.
  67
  68   resets:
  69     maxItems: 2
  70
  71   reset-names:
  72     minItems: 1
  73     maxItems: 2
  74     items:
  75       enum: [ qspi, qspi-ocp ]
  76
  77 # subnode's properties
  78 patternProperties:
  79   "@[0-9a-f]+$":
  80     type: object
  81     description:
  82       Flash device uses the below defined properties in the subnode.
  83
  84     properties:
  85       cdns,read-delay:
  86         $ref: /schemas/types.yaml#/definitions/uint32
  87         description:
  88           Delay for read capture logic, in clock cycles.
  89
  90       cdns,tshsl-ns:
  91         description:
  92           Delay in nanoseconds for the length that the master mode chip select
  93           outputs are de-asserted between transactions.
  94
  95       cdns,tsd2d-ns:
  96         description:
  97           Delay in nanoseconds between one chip select being de-activated
  98           and the activation of another.
  99
 100       cdns,tchsh-ns:
 101         description:
 102           Delay in nanoseconds between last bit of current transaction and
 103           deasserting the device chip select (qspi_n_ss_out).
 104
 105       cdns,tslch-ns:
 106         description:
 107           Delay in nanoseconds between setting qspi_n_ss_out low and
 108           first bit transfer.
 109
 110 required:
 111   - compatible
 112   - reg
 113   - interrupts
 114   - clocks
 115   - cdns,fifo-depth
 116   - cdns,fifo-width
 117   - cdns,trigger-address
 118   - '#address-cells'
 119   - '#size-cells'
 120
 121 unevaluatedProperties: false
 122
 123 examples:
 124   - |
 125     qspi: spi@ff705000 {
 126       compatible = "cdns,qspi-nor";
 127       #address-cells = <1>;
 128       #size-cells = <0>;
 129       reg = <0xff705000 0x1000>,
 130             <0xffa00000 0x1000>;
 131       interrupts = <0 151 4>;
 132       clocks = <&qspi_clk>;
 133       cdns,fifo-depth = <128>;
 134       cdns,fifo-width = <4>;
 135       cdns,trigger-address = <0x00000000>;
 136       resets = <&rst 0x1>, <&rst 0x2>;
 137       reset-names = "qspi", "qspi-ocp";
 138
 139       flash@0 {
 140               compatible = "jedec,spi-nor";
 141               reg = <0x0>;
 142       };
 143     };