1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
17 MSPI : SPI master controller can read and write to a SPI slave device
18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
19 for flash reads and be configured to do single, double, quad lane
20 io with 3-byte and 4-byte addressing support.
22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
23 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
24 of a MSPI master without the BSPI to use with non flash slave devices that
28 - $ref: spi-controller.yaml#
33 - description: Second Instance of MSPI BRCMSTB SoCs
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
43 - const: brcm,spi-brcmstb-mspi
44 - description: Second Instance of MSPI BRCMSTB SoCs
47 - brcm,spi-brcmstb-qspi
48 - brcm,spi-brcmstb-mspi
51 - const: brcm,spi-bcm-qspi
63 - enum: [ intr_regs, intr_status_reg, cs_reg ]
64 - enum: [ intr_regs, intr_status_reg, cs_reg ]
65 - enum: [ intr_regs, intr_status_reg, cs_reg ]
78 - const: spi_lr_fullness_reached
79 - const: spi_lr_session_aborted
80 - const: spi_lr_impatient
81 - const: spi_lr_session_done
82 - const: spi_lr_overread
87 description: reference clock for this block
90 $ref: /schemas/types.yaml#/definitions/flag
91 description: Defined when using BE SoC and device uses BE register read/write
93 unevaluatedProperties: false
102 - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
104 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
105 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
106 reg-names = "mspi", "bspi", "cs_reg";
107 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
108 interrupt-parent = <&gic>;
109 interrupt-names = "mspi_done",
111 "spi_lr_fullness_reached",
112 "spi_lr_session_aborted",
114 "spi_lr_session_done",
117 #address-cells = <0x1>;
122 #address-cells = <0x2>;
123 compatible = "m25p80";
125 spi-max-frequency = <0x2625a00>;
130 - | # BRCMSTB SoC: MSPI master for any SPI device
132 clocks = <&upg_fixed>;
133 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
134 reg = <0xf0416000 0x180>;
137 interrupt-parent = <&irq0_aon_intc>;
138 interrupt-names = "mspi_done";
139 #address-cells = <1>;
143 #include <dt-bindings/interrupt-controller/irq.h>
144 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
148 reg = <0x18027200 0x184>,
152 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
153 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-names = "mspi_done",
162 "spi_lr_fullness_reached",
163 "spi_lr_session_aborted",
165 "spi_lr_session_done";
166 clocks = <&iprocmed>;
168 #address-cells = <1>;
172 #include <dt-bindings/interrupt-controller/irq.h>
173 #include <dt-bindings/interrupt-controller/arm-gic.h>
176 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
177 reg = <0x66470200 0x184>,
181 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
182 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
183 interrupt-names = "spi_l1_intr";
184 clocks = <&iprocmed>;
186 #address-cells = <1>;
190 #address-cells = <1>;
192 compatible = "m25p80";
194 spi-max-frequency = <12500000>;