1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated
5 $id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Dan Murphy <dmurphy@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
17 family supports line and microphone Inputs, and offers a programmable
18 microphone bias or supply voltage generation.
20 Specifications can be found at:
21 https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
22 https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
23 https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
28 - const: ti,tlv320adc3140
29 - const: ti,tlv320adc5140
30 - const: ti,tlv320adc6140
35 I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
39 GPIO used for hardware reset.
43 Regulator with AVDD at 3.3V. If not defined then the internal regulator
48 Indicates the source for MIC Bias.
49 0 - Mic bias is set to VREF
50 1 - Mic bias is set to VREF × 1.096
51 6 - Mic bias is set to AVDD
52 $ref: /schemas/types.yaml#/definitions/uint32
57 Indicates the source for MIC Bias.
60 2 - Set VREF to 1.375V
61 $ref: /schemas/types.yaml#/definitions/uint32
66 Defines the PDMCLK sampling edge configuration for the PDM inputs. This
67 array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
69 0 - (default) Odd channel is latched on the negative edge and even
70 channel is latched on the the positive edge.
71 1 - Odd channel is latched on the positive edge and even channel is
72 latched on the the negative edge.
74 PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
75 PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
76 PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
77 PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
79 $ref: /schemas/types.yaml#/definitions/uint32-array
88 Defines the configuration for the general purpose input pins (GPI).
89 The array is defined as <GPI1 GPI2 GPI3 GPI4>.
91 0 - (default) disabled
92 1 - GPIX is configured as a general-purpose input (GPI)
93 2 - GPIX is configured as a master clock input (MCLK)
94 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
95 4 - GPIX is configured as a PDM data input for channel 1 and channel
97 5 - GPIX is configured as a PDM data input for channel 3 and channel
99 6 - GPIX is configured as a PDM data input for channel 5 and channel
101 7 - GPIX is configured as a PDM data input for channel 7 and channel
104 $ref: /schemas/types.yaml#/definitions/uint32-array
109 default: [0, 0, 0, 0]
112 '^ti,gpo-config-[1-4]$':
113 $ref: /schemas/types.yaml#/definitions/uint32-array
115 Defines the configuration and output driver for the general purpose
116 output pins (GPO). These values are pairs, the first value is for the
117 configuration type and the second value is for the output drive type.
118 The array is defined as <GPO_CFG GPO_DRV>
120 GPO output configuration can be one of the following:
122 0 - (default) disabled
123 1 - GPOX is configured as a general-purpose output (GPO)
124 2 - GPOX is configured as a device interrupt output (IRQ)
125 3 - GPOX is configured as a secondary ASI output (SDOUT2)
126 4 - GPOX is configured as a PDM clock output (PDMCLK)
128 GPO output drive configuration for the GPO pins can be one of the following:
130 0d - (default) Hi-Z output
131 1d - Drive active low and active high
132 2d - Drive active low and weak high
133 3d - Drive active low and Hi-Z
134 4d - Drive weak low and active high
135 5d - Drive Hi-Z and active high
143 #include <dt-bindings/gpio/gpio.h>
145 #address-cells = <1>;
148 compatible = "ti,tlv320adc5140";
150 ti,mic-bias-source = <6>;
151 ti,pdm-edge-select = <0 1 0 1>;
152 ti,gpi-config = <4 5 6 7>;
153 ti,gpo-config-1 = <0 0>;
154 ti,gpo-config-2 = <0 0>;
155 reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;