1 Freescale Synchronous Audio Interface (SAI).
3 The SAI is based on I2S module that used communicating with audio codecs,
4 which provides a synchronous audio interface that supports fullduplex
5 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
10 - compatible : Compatible list, contains "fsl,vf610-sai",
11 "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12 "fsl,imx7ulp-sai", "fsl,imx8mq-sai" or
15 - reg : Offset and length of the register set for the device.
17 - clocks : Must contain an entry for each entry in clock-names.
19 - clock-names : Must include the "bus" for register access and
20 "mclk1", "mclk2", "mclk3" for bit clock and frame
22 - dmas : Generic dma devicetree binding as described in
23 Documentation/devicetree/bindings/dma/dma.txt.
25 - dma-names : Two dmas have to be defined, "tx" and "rx".
27 - pinctrl-names : Must contain a "default" entry.
29 - pinctrl-NNN : One property must exist for each entry in
30 pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
31 for details of the property values.
33 - lsb-first : Configures whether the LSB or the MSB is transmitted
34 first for the fifo data. If this property is absent,
35 the MSB is transmitted first as default, or the LSB
38 - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
39 that SAI will work in the synchronous mode (sync Tx
40 with Rx) which means both the transmitter and the
41 receiver will send and receive data by following
42 receiver's bit clocks and frame sync clocks.
44 - fsl,sai-asynchronous: This is a boolean property. If present, indicating
45 that SAI will work in the asynchronous mode, which
46 means both transmitter and receiver will send and
47 receive data by following their own bit clocks and
48 frame sync clocks separately.
52 - big-endian : Boolean property, required if all the SAI
53 registers are big-endian rather than little-endian.
55 Optional properties (for mx6ul):
57 - fsl,sai-mclk-direction-output: This is a boolean property. If present,
58 indicates that SAI will output the SAI MCLK clock.
61 - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
62 default synchronous mode (sync Rx with Tx) will be used, which means both
63 transmitter and receiver will send and receive data by following clocks
65 - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
69 compatible = "fsl,vf610-sai";
70 reg = <0x40031000 0x1000>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_sai2_1>;
73 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
74 <&clks VF610_CLK_SAI2>,
76 clock-names = "bus", "mclk1", "mclk2", "mclk3";
77 dma-names = "tx", "rx";
78 dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
79 <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;