1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/fsl,xcvr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Audio Transceiver (XCVR) Controller
10 - Viorel Suman <viorel.suman@nxp.com>
13 NXP XCVR (Audio Transceiver) is a on-chip functional module
14 that allows CPU to receive and transmit digital audio via
15 HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.
27 - description: 20K RAM for code and data
28 - description: registers space
29 - description: RX FIFO address
30 - description: TX FIFO address
44 - description: Peripheral clock
45 - description: PHY clock
46 - description: SPBA clock
47 - description: PLL clock
58 - description: DMA controller phandle and request line for RX
59 - description: DMA controller phandle and request line for TX
80 additionalProperties: false
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 #include <dt-bindings/clock/imx8mp-clock.h>
86 #include <dt-bindings/reset/imx8mp-reset.h>
89 compatible = "fsl,imx8mp-xcvr";
90 reg = <0x30cc0000 0x800>,
94 reg-names = "ram", "regs", "rxfifo", "txfifo";
95 interrupts = <0x0 128 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
97 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
98 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
99 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
100 clock-names = "ipg", "phy", "spba", "pll_ipg";
101 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
102 dma-names = "rx", "tx";
103 resets = <&audiomix_reset 0>;