1 Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
3 The Freescale S/PDIF audio block is a stereo transceiver that allows the
4 processor to receive and transmit digital audio via an coaxial cable or
9 - compatible : Compatible list, must contain "fsl,imx35-spdif".
11 - reg : Offset and length of the register set for the device.
13 - interrupts : Contains the spdif interrupt.
15 - dmas : Generic dma devicetree binding as described in
16 Documentation/devicetree/bindings/dma/dma.txt.
18 - dma-names : Two dmas have to be defined, "tx" and "rx".
20 - clocks : Contains an entry for each entry in clock-names.
22 - clock-names : Includes the following entries:
23 "core" The core clock of spdif controller
24 "rxtx<0-7>" Clock source list for tx and rx clock.
25 This clock list should be identical to
26 the source list connecting to the spdif
27 clock mux in "SPDIF Transceiver Clock
28 Diagram" of SoC reference manual. It
29 can also be referred to TxClk_Source
30 bit of register SPDIF_STC.
32 - big-endian : If this property is absent, the native endian mode will
33 be in use as default, or the big endian mode will be in use for all the
38 spdif: spdif@02004000 {
39 compatible = "fsl,imx35-spdif";
40 reg = <0x02004000 0x4000>;
41 interrupts = <0 52 0x04>;
42 dmas = <&sdma 14 18 0>,
44 dma-names = "rx", "tx";
46 clocks = <&clks 197>, <&clks 3>,
47 <&clks 197>, <&clks 107>,
48 <&clks 0>, <&clks 118>,
49 <&clks 62>, <&clks 139>,
51 clock-names = "core", "rxtx0",