1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19 instruction RAMs, some internal peripheral modules to facilitate industrial
20 communication, and an interrupt controller.
22 The programmable nature of the PRUs provide flexibility to implement custom
23 peripheral interfaces, fast real-time responses, or specialized data handling.
24 The common peripheral modules include the following,
25 - an Ethernet MII_RT module with two MII ports
26 - an MDIO port to control external Ethernet PHYs
27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
29 - an Enhanced Capture Module (eCAP)
30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31 - a 16550-compatible UART to support PROFIBUS
32 - Enhanced GPIO with async capture and serial support
34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
40 RAM, and specific register spaces for Control and Debug functionalities.
42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
43 nodes and are defined using a parent-child hierarchy depending on their
44 integration within the IP and the SoC. These nodes are described in the
50 Each PRU-ICSS instance is represented as its own node with the individual PRU
51 processor cores, the memories node, an INTC node and an MDIO node represented
52 as child nodes within this PRUSS node. This node shall be a child of the
53 corresponding interconnect bus nodes or target-module nodes.
55 See ../../mfd/syscon.yaml for generic SysCon binding details.
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
64 - ti,am3356-pruss # for AM335x SoC family
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67 - ti,am5728-pruss # for AM57xx SoC family
68 - ti,am625-pruss # for K3 AM62x SoC family
69 - ti,am642-icssg # for K3 AM64x SoC family
70 - ti,am654-icssg # for K3 AM65x SoC family
71 - ti,j721e-icssg # for K3 J721E SoC family
72 - ti,k2g-pruss # for 66AK2G SoC family
93 This property is as per sci-pm-domain.txt.
99 The various Data RAMs within a single PRU-ICSS unit are represented as a
100 single node with the name 'memories'.
106 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
108 - description: Address and size of the Data RAM0.
109 - description: Address and size of the Data RAM1.
111 Address and size of the Shared Data RAM. Note that on AM437x one
112 of two PRUSS units don't contain Shared RAM, while the second one
126 additionalProperties: false
130 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
133 additionalProperties: false
138 - const: ti,pruss-cfg
164 coreclk-mux@[a-f0-9]+$:
166 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
167 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
168 ICSSG_ICLK. This node models this clock mux and should have the
179 - description: ICSSG_CORE Clock
180 - description: ICSSG_ICLK Clock
185 assigned-clock-parents:
188 Standard assigned-clocks-parents definition used for selecting
189 mux parent (one of the mux input).
197 additionalProperties: false
199 iepclk-mux@[a-f0-9]+$:
201 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
202 CORE_CLK (OCP_CLK in older SoCs). This node models this clock
203 mux and should have the name "iepclk-mux".
213 - description: ICSSG_IEP Clock
214 - description: Core Clock (OCP Clock in older SoCs)
219 assigned-clock-parents:
222 Standard assigned-clocks-parents definition used for selecting
223 mux parent (one of the mux input).
231 additionalProperties: false
233 additionalProperties: false
237 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
238 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
239 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs).
240 IEP is used for creating PTP clocks and generating PPS signals.
246 Real-Time Ethernet to support multiple industrial communication protocols.
247 MII-RT sub-module represented as a SysCon.
254 - const: ti,pruss-mii
260 additionalProperties: false
264 The Real-time Media Independent Interface to support multiple industrial
265 communication protocols (G stands for Gigabit). MII-G-RT sub-module
266 represented as a SysCon.
273 - const: ti,pruss-mii-g
279 additionalProperties: false
281 interrupt-controller@[a-f0-9]+$:
283 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
284 that is common to all the PRU cores. This should be represented as an
285 interrupt-controller node.
286 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
291 MDIO Node. Each PRUSS has an MDIO module that can be used to control
292 external PHYs. The MDIO module used within the PRU-ICSS is an instance of
293 the MDIO Controller used in TI Davinci SoCs.
294 $ref: /schemas/net/ti,davinci-mdio.yaml#
297 "^(pru|rtu|txpru)@[0-9a-f]+$":
299 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
300 device through a PRU child node each. Each node can optionally be rendered
301 inactive by using the standard DT string property, "status". The ICSSG IP
302 present on K3 SoCs have additional auxiliary PRU cores with slightly
303 different IP integration.
304 $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
312 additionalProperties: false
314 # Due to inability of correctly verifying sub-nodes with an @address through
315 # the "required" list, the required sub-nodes below are commented out for now.
319 # - interrupt-controller
349 /* Example 1 AM33xx PRU-ICSS */
351 compatible = "ti,am3356-pruss";
353 #address-cells = <1>;
357 pruss_mem: memories@0 {
361 reg-names = "dram0", "dram1", "shrdram2";
364 pruss_cfg: cfg@26000 {
365 compatible = "ti,pruss-cfg", "syscon";
366 #address-cells = <1>;
368 reg = <0x26000 0x2000>;
369 ranges = <0x00 0x26000 0x2000>;
372 #address-cells = <1>;
375 pruss_iepclk_mux: iepclk-mux@30 {
378 clocks = <&l3_gclk>, /* icss_iep */
379 <&pruss_ocp_gclk>; /* icss_ocp */
384 pruss_mii_rt: mii-rt@32000 {
385 compatible = "ti,pruss-mii", "syscon";
386 reg = <0x32000 0x58>;
389 pruss_intc: interrupt-controller@20000 {
390 compatible = "ti,pruss-intc";
391 reg = <0x20000 0x2000>;
392 interrupt-controller;
393 #interrupt-cells = <3>;
394 interrupts = <20 21 22 23 24 25 26 27>;
395 interrupt-names = "host_intr0", "host_intr1",
396 "host_intr2", "host_intr3",
397 "host_intr4", "host_intr5",
398 "host_intr6", "host_intr7";
402 compatible = "ti,am3356-pru";
403 reg = <0x34000 0x2000>,
406 reg-names = "iram", "control", "debug";
407 firmware-name = "am335x-pru0-fw";
411 compatible = "ti,am3356-pru";
412 reg = <0x38000 0x2000>,
415 reg-names = "iram", "control", "debug";
416 firmware-name = "am335x-pru1-fw";
419 pruss_mdio: mdio@32400 {
420 compatible = "ti,davinci_mdio";
421 reg = <0x32400 0x90>;
422 clocks = <&dpll_core_m4_ck>;
424 bus_freq = <1000000>;
425 #address-cells = <1>;
432 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
433 #include <dt-bindings/interrupt-controller/arm-gic.h>
435 compatible = "ti,am4376-pruss1";
437 #address-cells = <1>;
441 pruss1_mem: memories@0 {
445 reg-names = "dram0", "dram1", "shrdram2";
448 pruss1_cfg: cfg@26000 {
449 compatible = "ti,pruss-cfg", "syscon";
450 #address-cells = <1>;
452 reg = <0x26000 0x2000>;
453 ranges = <0x00 0x26000 0x2000>;
456 #address-cells = <1>;
459 pruss1_iepclk_mux: iepclk-mux@30 {
462 clocks = <&sysclk_div>, /* icss_iep */
463 <&pruss_ocp_gclk>; /* icss_ocp */
468 pruss1_mii_rt: mii-rt@32000 {
469 compatible = "ti,pruss-mii", "syscon";
470 reg = <0x32000 0x58>;
473 pruss1_intc: interrupt-controller@20000 {
474 compatible = "ti,pruss-intc";
475 reg = <0x20000 0x2000>;
476 interrupt-controller;
477 #interrupt-cells = <3>;
478 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "host_intr0", "host_intr1",
486 "host_intr2", "host_intr3",
488 "host_intr6", "host_intr7";
489 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
493 compatible = "ti,am4376-pru";
494 reg = <0x34000 0x3000>,
497 reg-names = "iram", "control", "debug";
498 firmware-name = "am437x-pru1_0-fw";
502 compatible = "ti,am4376-pru";
503 reg = <0x38000 0x3000>,
506 reg-names = "iram", "control", "debug";
507 firmware-name = "am437x-pru1_1-fw";
510 pruss1_mdio: mdio@32400 {
511 compatible = "ti,davinci_mdio";
512 reg = <0x32400 0x90>;
513 clocks = <&dpll_core_m4_ck>;
515 bus_freq = <1000000>;
516 #address-cells = <1>;