1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19 instruction RAMs, some internal peripheral modules to facilitate industrial
20 communication, and an interrupt controller.
22 The programmable nature of the PRUs provide flexibility to implement custom
23 peripheral interfaces, fast real-time responses, or specialized data handling.
24 The common peripheral modules include the following,
25 - an Ethernet MII_RT module with two MII ports
26 - an MDIO port to control external Ethernet PHYs
27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
29 - an Enhanced Capture Module (eCAP)
30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31 - a 16550-compatible UART to support PROFIBUS
32 - Enhanced GPIO with async capture and serial support
34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
40 RAM, and specific register spaces for Control and Debug functionalities.
42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
43 nodes and are defined using a parent-child hierarchy depending on their
44 integration within the IP and the SoC. These nodes are described in the
50 Each PRU-ICSS instance is represented as its own node with the individual PRU
51 processor cores, the memories node, an INTC node and an MDIO node represented
52 as child nodes within this PRUSS node. This node shall be a child of the
53 corresponding interconnect bus nodes or target-module nodes.
55 See ../../mfd/syscon.yaml for generic SysCon binding details.
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
64 - ti,am3356-pruss # for AM335x SoC family
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67 - ti,am5728-pruss # for AM57xx SoC family
68 - ti,k2g-pruss # for 66AK2G SoC family
69 - ti,am654-icssg # for K3 AM65x SoC family
70 - ti,j721e-icssg # for K3 J721E SoC family
89 This property is as per sci-pm-domain.txt.
95 The various Data RAMs within a single PRU-ICSS unit are represented as a
96 single node with the name 'memories'.
102 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
104 - description: Address and size of the Data RAM0.
105 - description: Address and size of the Data RAM1.
107 Address and size of the Shared Data RAM. Note that on AM437x one
108 of two PRUSS units don't contain Shared RAM, while the second one
122 additionalProperties: false
126 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
133 - const: ti,pruss-cfg
159 coreclk-mux@[a-f0-9]+$:
161 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
162 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
163 ICSSG_ICLK. This node models this clock mux and should have the
174 - description: ICSSG_CORE Clock
175 - description: ICSSG_ICLK Clock
180 assigned-clock-parents:
183 Standard assigned-clocks-parents definition used for selecting
184 mux parent (one of the mux input).
192 additionalProperties: false
194 iepclk-mux@[a-f0-9]+$:
196 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
197 CORE_CLK (OCP_CLK in older SoCs). This node models this clock
198 mux and should have the name "iepclk-mux".
208 - description: ICSSG_IEP Clock
209 - description: Core Clock (OCP Clock in older SoCs)
214 assigned-clock-parents:
217 Standard assigned-clocks-parents definition used for selecting
218 mux parent (one of the mux input).
226 additionalProperties: false
228 additionalProperties: false
232 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
233 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
234 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP
235 is used for creating PTP clocks and generating PPS signals.
241 Real-Time Ethernet to support multiple industrial communication protocols.
242 MII-RT sub-module represented as a SysCon.
249 - const: ti,pruss-mii
255 additionalProperties: false
259 The Real-time Media Independent Interface to support multiple industrial
260 communication protocols (G stands for Gigabit). MII-G-RT sub-module
261 represented as a SysCon.
268 - const: ti,pruss-mii-g
274 additionalProperties: false
276 interrupt-controller@[a-f0-9]+$:
278 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
279 that is common to all the PRU cores. This should be represented as an
280 interrupt-controller node.
283 - $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
289 MDIO Node. Each PRUSS has an MDIO module that can be used to control
290 external PHYs. The MDIO module used within the PRU-ICSS is an instance of
291 the MDIO Controller used in TI Davinci SoCs.
294 - $ref: /schemas/net/ti,davinci-mdio.yaml#
298 "^(pru|rtu|txpru)@[0-9a-f]+$":
300 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
301 device through a PRU child node each. Each node can optionally be rendered
302 inactive by using the standard DT string property, "status". The ICSSG IP
303 present on K3 SoCs have additional auxiliary PRU cores with slightly
304 different IP integration.
307 - $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
316 additionalProperties: false
318 # Due to inability of correctly verifying sub-nodes with an @address through
319 # the "required" list, the required sub-nodes below are commented out for now.
323 # - interrupt-controller
341 /* Example 1 AM33xx PRU-ICSS */
343 compatible = "ti,am3356-pruss";
345 #address-cells = <1>;
349 pruss_mem: memories@0 {
353 reg-names = "dram0", "dram1", "shrdram2";
356 pruss_cfg: cfg@26000 {
357 compatible = "ti,pruss-cfg", "syscon";
358 #address-cells = <1>;
360 reg = <0x26000 0x2000>;
361 ranges = <0x00 0x26000 0x2000>;
364 #address-cells = <1>;
367 pruss_iepclk_mux: iepclk-mux@30 {
370 clocks = <&l3_gclk>, /* icss_iep */
371 <&pruss_ocp_gclk>; /* icss_ocp */
376 pruss_mii_rt: mii-rt@32000 {
377 compatible = "ti,pruss-mii", "syscon";
378 reg = <0x32000 0x58>;
381 pruss_intc: interrupt-controller@20000 {
382 compatible = "ti,pruss-intc";
383 reg = <0x20000 0x2000>;
384 interrupt-controller;
385 #interrupt-cells = <3>;
386 interrupts = <20 21 22 23 24 25 26 27>;
387 interrupt-names = "host_intr0", "host_intr1",
388 "host_intr2", "host_intr3",
389 "host_intr4", "host_intr5",
390 "host_intr6", "host_intr7";
394 compatible = "ti,am3356-pru";
395 reg = <0x34000 0x2000>,
398 reg-names = "iram", "control", "debug";
399 firmware-name = "am335x-pru0-fw";
403 compatible = "ti,am3356-pru";
404 reg = <0x38000 0x2000>,
407 reg-names = "iram", "control", "debug";
408 firmware-name = "am335x-pru1-fw";
411 pruss_mdio: mdio@32400 {
412 compatible = "ti,davinci_mdio";
413 reg = <0x32400 0x90>;
414 clocks = <&dpll_core_m4_ck>;
416 bus_freq = <1000000>;
417 #address-cells = <1>;
424 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
425 #include <dt-bindings/interrupt-controller/arm-gic.h>
427 compatible = "ti,am4376-pruss1";
429 #address-cells = <1>;
433 pruss1_mem: memories@0 {
437 reg-names = "dram0", "dram1", "shrdram2";
440 pruss1_cfg: cfg@26000 {
441 compatible = "ti,pruss-cfg", "syscon";
442 #address-cells = <1>;
444 reg = <0x26000 0x2000>;
445 ranges = <0x00 0x26000 0x2000>;
448 #address-cells = <1>;
451 pruss1_iepclk_mux: iepclk-mux@30 {
454 clocks = <&sysclk_div>, /* icss_iep */
455 <&pruss_ocp_gclk>; /* icss_ocp */
460 pruss1_mii_rt: mii-rt@32000 {
461 compatible = "ti,pruss-mii", "syscon";
462 reg = <0x32000 0x58>;
465 pruss1_intc: interrupt-controller@20000 {
466 compatible = "ti,pruss-intc";
467 reg = <0x20000 0x2000>;
468 interrupt-controller;
469 #interrupt-cells = <3>;
470 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "host_intr0", "host_intr1",
478 "host_intr2", "host_intr3",
480 "host_intr6", "host_intr7";
481 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
485 compatible = "ti,am4376-pru";
486 reg = <0x34000 0x3000>,
489 reg-names = "iram", "control", "debug";
490 firmware-name = "am437x-pru1_0-fw";
494 compatible = "ti,am4376-pru";
495 reg = <0x38000 0x3000>,
498 reg-names = "iram", "control", "debug";
499 firmware-name = "am437x-pru1_1-fw";
502 pruss1_mdio: mdio@32400 {
503 compatible = "ti,davinci_mdio";
504 reg = <0x32400 0x90>;
505 clocks = <&dpll_core_m4_ck>;
507 bus_freq = <1000000>;
508 #address-cells = <1>;