1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <festevam@gmail.com>
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
31 - const: fsl,imx21-uart
37 - const: fsl,imx6q-uart
38 - const: fsl,imx21-uart
47 - const: fsl,imx6q-uart
62 - description: DMA controller phandle and request line for RX
63 - description: DMA controller phandle and request line for TX
74 $ref: /schemas/types.yaml#/definitions/flag
76 Indicate the uart works in DTE mode. The uart works in DCE mode by default.
79 $ref: /schemas/types.yaml#/definitions/flag
81 Indicate that the hardware attached to the peripheral inverts the signal
82 transmitted, and that the peripheral should invert its output using the
86 $ref: /schemas/types.yaml#/definitions/flag
88 Indicate that the hardware attached to the peripheral inverts the signal
89 received, and that the peripheral should invert its input using the
93 $ref: /schemas/types.yaml#/definitions/uint32-array
97 First cell contains the size of DMA buffer chunks, second cell contains
98 the amount of chunks used for the device. Multiplying both numbers is
99 the total size of memory used for receiving data.
100 When not being configured the system will use default settings, which
101 are sensible for most use cases. If you need low latency processing on
102 slow connections this needs to be configured appropriately.
111 unevaluatedProperties: false
115 #include <dt-bindings/clock/imx5-clock.h>
121 uart1: serial@73fbc000 {
122 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
123 reg = <0x73fbc000 0x4000>;
125 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
126 <&clks IMX5_CLK_UART1_PER_GATE>;
127 clock-names = "ipg", "per";
128 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
129 dma-names = "rx", "tx";