1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
19 - aspeed,lpc-interrupts
21 - aspeed,sirq-polarity-sense
25 const: aspeed,ast2500-vuart
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nvidia,tegra20-uart
66 - const: nxp,lpc3220-uart
76 - opencores,uart16550-rtlsvn105
82 - cavium,octeon-3860-uart
83 - xlnx,xps-uart16550-2.00.b
86 - ns16550 # Deprecated, unless the FIFO really is broken
93 - const: ralink,rt2880-uart
95 - ns16550 # Deprecated, unless the FIFO really is broken
99 - mediatek,mt7622-btif
100 - mediatek,mt7623-btif
101 - const: mediatek,mtk-btif
104 - mediatek,mt7622-btif
105 - mediatek,mt7623-btif
106 - const: mediatek,mtk-btif
108 - const: mrvl,mmp-uart
109 - const: intel,xscale-uart
112 - nvidia,tegra30-uart
113 - nvidia,tegra114-uart
114 - nvidia,tegra124-uart
115 - nvidia,tegra186-uart
116 - nvidia,tegra194-uart
117 - nvidia,tegra210-uart
118 - const: nvidia,tegra20-uart
126 clock-frequency: true
135 $ref: /schemas/types.yaml#/definitions/uint32
136 description: The current active speed of the UART.
140 Offset to apply to the mapbase from the start of the registers.
143 description: Quantity to shift the register offsets by.
147 The size (in bytes) of the IO accesses that should be performed on the
148 device. There are some systems that require 32-bit accesses to the
149 UART (e.g. TI davinci).
154 Set to indicate that the port is in use by the OpenFirmware RTAS and
155 should not be registered.
160 Set to indicate that the port does not implement loopback test mode.
163 $ref: /schemas/types.yaml#/definitions/uint32
164 description: The fifo size of the UART.
169 One way to enable automatic flow control support. The driver is
170 allowed to detect support for the capability even without this
175 Specify the TX FIFO low water indication for parts with programmable
180 How long to pause uart rx when input overrun is encountered.
189 aspeed,sirq-polarity-sense:
190 $ref: /schemas/types.yaml#/definitions/phandle-array
192 Phandle to aspeed,ast2500-scu compatible syscon alongside register
193 offset and bit number to identify how the SIRQ polarity should be
194 configured. One possible data source is the LPC/eSPI mode bit. Only
195 applicable to aspeed,ast2500-vuart.
199 $ref: '/schemas/types.yaml#/definitions/uint32'
201 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
203 aspeed,lpc-interrupts:
204 $ref: "/schemas/types.yaml#/definitions/uint32-array"
208 A 2-cell property describing the VUART SIRQ number and SIRQ
209 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
210 applicable to aspeed,ast2500-vuart.
216 unevaluatedProperties: false
221 compatible = "ns8250";
222 reg = <0x80230000 0x100>;
225 clock-frequency = <48000000>;
228 #include <dt-bindings/gpio/gpio.h>
230 compatible = "andestech,uart16550", "ns16550a";
231 reg = <0x49042000 0x400>;
233 clock-frequency = <48000000>;
234 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
235 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
236 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
237 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
238 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
239 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
242 #include <dt-bindings/clock/aspeed-clock.h>
243 #include <dt-bindings/interrupt-controller/irq.h>
245 compatible = "aspeed,ast2500-vuart";
246 reg = <0x1e787000 0x40>;
249 clocks = <&syscon ASPEED_CLK_APB>;
251 aspeed,lpc-io-reg = <0x3f8>;
252 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;