1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
43 - required: [ clock-frequency ]
44 - required: [ clocks ]
54 - const: aspeed,ast2400-vuart
55 - const: aspeed,ast2500-vuart
56 - const: intel,xscale-uart
57 - const: mrvl,pxa-uart
58 - const: nuvoton,npcm750-uart
59 - const: nvidia,tegra20-uart
60 - const: nxp,lpc3220-uart
70 - opencores,uart16550-rtlsvn105
76 - cavium,octeon-3860-uart
77 - xlnx,xps-uart16550-2.00.b
80 - ns16550 # Deprecated, unless the FIFO really is broken
87 - const: ralink,rt2880-uart
89 - ns16550 # Deprecated, unless the FIFO really is broken
93 - mediatek,mt7622-btif
94 - mediatek,mt7623-btif
95 - const: mediatek,mtk-btif
98 - mediatek,mt7622-btif
99 - mediatek,mt7623-btif
100 - const: mediatek,mtk-btif
102 - const: mrvl,mmp-uart
103 - const: intel,xscale-uart
106 - nvidia,tegra30-uart
107 - nvidia,tegra114-uart
108 - nvidia,tegra124-uart
109 - nvidia,tegra186-uart
110 - nvidia,tegra194-uart
111 - nvidia,tegra210-uart
112 - const: nvidia,tegra20-uart
120 clock-frequency: true
129 $ref: /schemas/types.yaml#/definitions/uint32
130 description: The current active speed of the UART.
134 Offset to apply to the mapbase from the start of the registers.
137 description: Quantity to shift the register offsets by.
141 The size (in bytes) of the IO accesses that should be performed on the
142 device. There are some systems that require 32-bit accesses to the
143 UART (e.g. TI davinci).
148 Set to indicate that the port is in use by the OpenFirmware RTAS and
149 should not be registered.
154 Set to indicate that the port does not implement loopback test mode.
157 $ref: /schemas/types.yaml#/definitions/uint32
158 description: The fifo size of the UART.
163 One way to enable automatic flow control support. The driver is
164 allowed to detect support for the capability even without this
168 $ref: /schemas/types.yaml#/definitions/uint32
170 Specify the TX FIFO low water indication for parts with programmable
175 How long to pause uart rx when input overrun is encountered.
184 aspeed,sirq-polarity-sense:
185 $ref: /schemas/types.yaml#/definitions/phandle-array
187 Phandle to aspeed,ast2500-scu compatible syscon alongside register
188 offset and bit number to identify how the SIRQ polarity should be
189 configured. One possible data source is the LPC/eSPI mode bit. Only
190 applicable to aspeed,ast2500-vuart.
196 unevaluatedProperties: false
201 compatible = "ns8250";
202 reg = <0x80230000 0x100>;
205 clock-frequency = <48000000>;
208 #include <dt-bindings/gpio/gpio.h>
210 compatible = "andestech,uart16550", "ns16550a";
211 reg = <0x49042000 0x400>;
213 clock-frequency = <48000000>;
214 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
215 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
216 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
217 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
218 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
219 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
222 #include <dt-bindings/clock/aspeed-clock.h>
224 compatible = "aspeed,ast2500-vuart";
225 reg = <0x1e787000 0x40>;
228 clocks = <&syscon ASPEED_CLK_APB>;
230 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;