1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
18 acts as directory-based coherency manager.
19 All the properties in ePAPR/DeviceTree specification applies for this platform.
22 - $ref: /schemas/cache-controller.yaml#
29 - sifive,fu540-c000-ccache
30 - sifive,fu740-c000-ccache
39 - sifive,fu540-c000-ccache
40 - sifive,fu740-c000-ccache
60 - description: DirError interrupt
61 - description: DataError interrupt
62 - description: DataFail interrupt
63 - description: DirFail interrupt
68 next-level-cache: true
73 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
74 The reserved memory node should be defined as per the bindings in reserved-memory.txt.
80 const: sifive,fu540-c000-ccache
86 Must contain entries for DirError, DataError and DataFail signals.
93 Must contain entries for DirError, DataError, DataFail, DirFail signals.
96 additionalProperties: false
110 cache-controller@2010000 {
111 compatible = "sifive,fu540-c000-ccache", "cache";
112 cache-block-size = <64>;
115 cache-size = <2097152>;
117 reg = <0x2010000 0x1000>;
118 interrupt-parent = <&plic0>;
122 next-level-cache = <&L25>;
123 memory-region = <&l2_lim>;