Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) 2020 SiFive, Inc.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: SiFive Composable Cache Controller
   9
  10 maintainers:
  11   - Paul Walmsley <paul.walmsley@sifive.com>
  12
  13 description:
  14   The SiFive Composable Cache Controller is used to provide access to fast copies
  15   of memory for masters in a Core Complex. The Composable Cache Controller also
  16   acts as directory-based coherency manager.
  17   All the properties in ePAPR/DeviceTree specification applies for this platform.
  18
  19 select:
  20   properties:
  21     compatible:
  22       contains:
  23         enum:
  24           - sifive,ccache0
  25           - sifive,fu540-c000-ccache
  26           - sifive,fu740-c000-ccache
  27
  28   required:
  29     - compatible
  30
  31 properties:
  32   compatible:
  33     oneOf:
  34       - items:
  35           - enum:
  36               - sifive,ccache0
  37               - sifive,fu540-c000-ccache
  38               - sifive,fu740-c000-ccache
  39           - const: cache
  40       - items:
  41           - const: microchip,mpfs-ccache
  42           - const: sifive,fu540-c000-ccache
  43           - const: cache
  44
  45   cache-block-size:
  46     const: 64
  47
  48   cache-level:
  49     enum: [2, 3]
  50
  51   cache-sets:
  52     enum: [1024, 2048]
  53
  54   cache-size:
  55     const: 2097152
  56
  57   cache-unified: true
  58
  59   interrupts:
  60     minItems: 3
  61     items:
  62       - description: DirError interrupt
  63       - description: DataError interrupt
  64       - description: DataFail interrupt
  65       - description: DirFail interrupt
  66
  67   reg:
  68     maxItems: 1
  69
  70   next-level-cache: true
  71
  72   memory-region:
  73     maxItems: 1
  74     description: |
  75       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
  76       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
  77
  78 allOf:
  79   - $ref: /schemas/cache-controller.yaml#
  80
  81   - if:
  82       properties:
  83         compatible:
  84           contains:
  85             enum:
  86               - sifive,fu740-c000-ccache
  87               - microchip,mpfs-ccache
  88
  89     then:
  90       properties:
  91         interrupts:
  92           description: |
  93             Must contain entries for DirError, DataError, DataFail, DirFail signals.
  94           minItems: 4
  95
  96     else:
  97       properties:
  98         interrupts:
  99           description: |
 100             Must contain entries for DirError, DataError and DataFail signals.
 101           maxItems: 3
 102
 103   - if:
 104       properties:
 105         compatible:
 106           contains:
 107             const: sifive,fu740-c000-ccache
 108
 109     then:
 110       properties:
 111         cache-sets:
 112           const: 2048
 113
 114     else:
 115       properties:
 116         cache-sets:
 117           const: 1024
 118
 119   - if:
 120       properties:
 121         compatible:
 122           contains:
 123             const: sifive,ccache0
 124
 125     then:
 126       properties:
 127         cache-level:
 128           enum: [2, 3]
 129
 130     else:
 131       properties:
 132         cache-level:
 133           const: 2
 134
 135 additionalProperties: false
 136
 137 required:
 138   - compatible
 139   - cache-block-size
 140   - cache-level
 141   - cache-sets
 142   - cache-size
 143   - cache-unified
 144   - interrupts
 145   - reg
 146
 147 examples:
 148   - |
 149     cache-controller@2010000 {
 150         compatible = "sifive,fu540-c000-ccache", "cache";
 151         cache-block-size = <64>;
 152         cache-level = <2>;
 153         cache-sets = <1024>;
 154         cache-size = <2097152>;
 155         cache-unified;
 156         reg = <0x2010000 0x1000>;
 157         interrupt-parent = <&plic0>;
 158         interrupts = <1>,
 159                      <2>,
 160                      <3>;
 161         next-level-cache = <&L25>;
 162         memory-region = <&l2_lim>;
 163     };