1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
15 that is not widely used, the definitions of which are listed here:
17 hart: A hardware execution context, which contains all the state
18 mandated by the RISC-V ISA: a PC and some registers. This
19 terminology is designed to disambiguate software's view of execution
20 contexts from any particular microarchitectural implementation
21 strategy. For example, an Intel laptop containing one socket with
22 two cores, each of which has two hyperthreads, could be described as
46 - const: sifive,rocket0
48 - const: riscv # Simulator only
50 Identifies that the hart uses the RISC-V instruction set
51 and identifies the type of the hart.
55 Identifies the MMU address translation mode used on this
56 hart. These values originate from the RISC-V Privileged
57 Specification document, available from
58 https://riscv.org/specifications/
59 $ref: "/schemas/types.yaml#/definitions/string"
68 Identifies the specific RISC-V instruction set architecture
69 supported by the hart. These are documented in the RISC-V
70 User-Level ISA document, available from
71 https://riscv.org/specifications/
73 While the isa strings in ISA specification are case
74 insensitive, letters in the riscv,isa string must be all
75 lowercase to simplify parsing.
76 $ref: "/schemas/types.yaml#/definitions/string"
81 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
82 timebase-frequency: false
86 description: Describes the CPU's local interrupt controller
95 interrupt-controller: true
100 - interrupt-controller
103 $ref: '/schemas/types.yaml#/definitions/phandle-array'
105 List of phandles to idle state nodes supported
106 by this hart (see ./idle-states.yaml).
110 - interrupt-controller
112 additionalProperties: true
116 // Example 1: SiFive Freedom U540G Development Kit
118 #address-cells = <1>;
120 timebase-frequency = <1000000>;
122 clock-frequency = <0>;
123 compatible = "sifive,rocket0", "riscv";
125 i-cache-block-size = <64>;
126 i-cache-sets = <128>;
127 i-cache-size = <16384>;
129 riscv,isa = "rv64imac";
130 cpu_intc0: interrupt-controller {
131 #interrupt-cells = <1>;
132 compatible = "riscv,cpu-intc";
133 interrupt-controller;
137 clock-frequency = <0>;
138 compatible = "sifive,rocket0", "riscv";
139 d-cache-block-size = <64>;
141 d-cache-size = <32768>;
145 i-cache-block-size = <64>;
147 i-cache-size = <32768>;
150 mmu-type = "riscv,sv39";
152 riscv,isa = "rv64imafdc";
154 cpu_intc1: interrupt-controller {
155 #interrupt-cells = <1>;
156 compatible = "riscv,cpu-intc";
157 interrupt-controller;
163 // Example 2: Spike ISA Simulator with 1 Hart
165 #address-cells = <1>;
170 compatible = "riscv";
171 riscv,isa = "rv64imafdc";
172 mmu-type = "riscv,sv48";
173 interrupt-controller {
174 #interrupt-cells = <1>;
175 interrupt-controller;
176 compatible = "riscv,cpu-intc";