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2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
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4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
9 Please also refer to reset.txt in this directory for common reset
10 controller binding usage.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
23 zynqmp_firmware: zynqmp-firmware {
24 compatible = "xlnx,zynqmp-firmware";
27 zynqmp_reset: reset-controller {
28 compatible = "xlnx,zynqmp-reset";
34 Specifying reset lines connected to IP modules
35 ==============================================
37 Device nodes that need access to reset lines should
38 specify them as a reset phandle in their corresponding node as
39 specified in reset.txt.
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
42 <dt-bindings/reset/xlnx-zynqmp-resets.h>
43 For list of all valid reset indices for Versal see
44 <dt-bindings/reset/xlnx-versal-resets.h>
48 serdes: zynqmp_phy@fd400000 {
51 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
52 reset-names = "sata_rst";