1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon System Reset Controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 Please also refer to reset.txt in this directory for common reset
14 controller binding usage.
15 The reset controller registers are part of the system-ctl block on
16 hi3660 and hi3670 SoCs.
22 - const: hisilicon,hi3660-reset
24 - const: hisilicon,hi3670-reset
25 - const: hisilicon,hi3660-reset
28 description: phandle of the reset's syscon.
29 $ref: /schemas/types.yaml#/definitions/phandle
33 Specifies the number of cells needed to encode a reset source.
34 Cell #1 : offset of the reset assert control register from the syscon
36 offset + 4: deassert control register
37 offset + 8: status control register
38 Cell #2 : bit position of the reset in the reset control register
44 additionalProperties: false
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/clock/hi3660-clock.h>
52 iomcu: iomcu@ffd7e000 {
53 compatible = "hisilicon,hi3660-iomcu", "syscon";
54 reg = <0xffd7e000 0x1000>;
57 iomcu_rst: iomcu_rst_controller {
58 compatible = "hisilicon,hi3660-reset";
59 hisilicon,rst-syscon = <&iomcu>;
63 /* Specifying reset lines connected to IP modules */
65 compatible = "snps,designware-i2c";
66 reg = <0xffd71000 0x1000>;
67 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
70 clock-frequency = <400000>;
71 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
72 resets = <&iomcu_rst 0x20 3>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;