1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/mtk,scp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
24 - mediatek,mt8195-scp-dual
28 Should contain the address ranges for memory regions SRAM, CFG, and,
29 on some platforms, L1TCM.
39 Clock for co-processor (see ../clock/clock-bindings.txt).
40 Required by mt8183 and mt8192.
50 $ref: /schemas/types.yaml#/definitions/string
52 If present, name (or relative path) of the file within the
53 firmware search path containing the firmware image used when
60 $ref: /schemas/mfd/google,cros-ec.yaml
62 This subnode represents the rpmsg device. The properties
63 of this node are defined by the individual bindings for
69 unevaluatedProperties: false
79 Standard ranges definition providing address translations for
80 local SCP SRAM address spaces to bus addresses.
86 The MediaTek SCP integrated to SoC might be a multi-core version.
87 The other cores are represented as child nodes of the boot core.
88 There are some integration differences for the IP like the usage of
89 address translator for translating SoC bus addresses into address space
92 Each SCP core has own cache memory. The SRAM and L1TCM are shared by
93 cores. The power of cache, SRAM and L1TCM power should be enabled
94 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
97 The SCP cores do not use an MMU, but has a set of registers to
98 control the translations between 32-bit CPU addresses into system bus
99 addresses. Cache and memory access settings are provided through a
100 Memory Protection Unit (MPU), programmable only from the SCP.
108 description: The base address and size of SRAM.
118 $ref: /schemas/types.yaml#/definitions/string
120 If present, name (or relative path) of the file within the
121 firmware search path containing the firmware image used when
122 initializing sub cores of multi-core SCP.
128 $ref: /schemas/mfd/google,cros-ec.yaml
130 This subnode represents the rpmsg device. The properties
131 of this node are defined by the individual bindings for
135 - mediatek,rpmsg-name
137 unevaluatedProperties: false
144 additionalProperties: false
156 - mediatek,mt8183-scp
157 - mediatek,mt8192-scp
167 - mediatek,mt8183-scp
168 - mediatek,mt8186-scp
169 - mediatek,mt8188-scp
182 - mediatek,mt8192-scp
183 - mediatek,mt8195-scp
197 - mediatek,mt8195-scp-dual
207 additionalProperties: false
211 #include <dt-bindings/clock/mt8192-clk.h>
214 compatible = "mediatek,mt8192-scp";
215 reg = <0x10500000 0x80000>,
217 <0x10720000 0xe0000>;
218 reg-names = "sram", "cfg", "l1tcm";
219 clocks = <&infracfg CLK_INFRA_SCPSYS>;
220 clock-names = "main";
223 compatible = "google,cros-ec-rpmsg";
224 mediatek,rpmsg-name = "cros-ec-rpmsg";
230 compatible = "mediatek,mt8195-scp-dual";
231 reg = <0x10720000 0xe0000>,
233 reg-names = "cfg", "l1tcm";
235 #address-cells = <1>;
237 ranges = <0 0x10500000 0x100000>;
240 compatible = "mediatek,scp-core";
245 compatible = "google,cros-ec-rpmsg";
246 mediatek,rpmsg-name = "cros-ec-rpmsg";
251 compatible = "mediatek,scp-core";
252 reg = <0xa0000 0x20000>;
256 compatible = "google,cros-ec-rpmsg";
257 mediatek,rpmsg-name = "cros-ec-rpmsg";